Patents by Inventor Gabriella Borionetti

Gabriella Borionetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
    Patent number: 8026145
    Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: September 27, 2011
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Gabriella Borionetti
  • ARSENIC AND PHOSPHORUS DOPED SILICON WAFER SUBSTRATES HAVING INTRINSIC GETTERING
    Publication number: 20090130824
    Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
    Type: Application
    Filed: December 31, 2008
    Publication date: May 21, 2009
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Gabriella Borionetti
  • Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
    Patent number: 7485928
    Abstract: A process for the preparation of low resistivity arsensic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: February 3, 2009
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Gabriella Borionetti
  • Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
    Publication number: 20070105279
    Abstract: A process for the preparation of low resistivity arsensic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 10, 2007
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Robert Falster, Vladimir Voronkov, Gabriella Borionetti
  • Method for detecting sources of contamination in silicon using a contamination monitor wafer
    Patent number: 5418172
    Abstract: A method for detecting transition metal contamination in or on equipment and fluids used or being evaluated for use in the manufacture, handling, or shipping of silicon wafers and electronic devices manufactured on silicon wafers. A contamination monitor wafer having an average minority carrier lifetime greater than about 250 microseconds is processed using one or more pieces of equipment or fluids. As part of, or subsequent to the processing step, the contamination monitor wafer is exposed to a temperature of at least 600.degree. C. and the minority carrier lifetime values of the contamination monitor wafer is thereafter determined. To insure that the recombination process is dot dominated by the effects of oxygen precipitates, the contamination monitor wafer should have an oxygen precipitate density of less than 10.sup.8 oxygen precipitates per cubic centimeter before and after being exposed to said temperature of at least 600.degree. C.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: May 23, 1995
    Assignee: MEMC Electronic Materials S.p.A.
    Inventors: Robert Falster, Gabriella Borionetti, Robert A. Craven