Abstract: A selective silicidation process for electronic devices that are integrated on a semiconductor substrate is presented. The devices have a number of active elements formed with gate region that has at least one polysilicon layer. The process begins with depositing a dielectric layer over the entire surface of the semiconductor. Then portions of the dielectric layer are removed to expose the polysilicon layer in the gate regions. Next, a layer of a transition metal is deposited and subjected to a thermal treatment for selectively reacting it with the polysilicon layers and producing a silicide layer over the gate regions.

Abstract: A process creates contacts in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure. The cross-point structure includes memory cell matrices in which the bit lines are parallel unbroken diffusion strips extending along a column of the matrix with the contacts being provided through associated contact apertures defined through a dielectric layer deposited over a contact region defined on a semiconductor substrate at one end of the bit lines. The process calls for a step of implantation and following diffusion of contact areas provided in the substrate at opposite sides of each bit line to be contacted to widen the area designed to receive the contacts.

Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.

Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.

Abstract: Disclosed is an electrically alterable, floating gate type, nonvolatile, semiconductor memory device wherein the gate oxide layer in the "injection" area between the silicon (drain region of the device) and the floating gate has an increased thickness with respect to the thickness of the same gate oxide layer over the channel region of the device in order to decrease the parasitic capacitance of the injection area, thus improving the programming threshold voltage characteristics. A method for fabricating the improved memory device is also disclosed.