Patents by Inventor Gabriella Ghidini
Gabriella Ghidini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11302471Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: GrantFiled: January 16, 2020Date of Patent: April 12, 2022Assignee: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Fausto Renzo Toia
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Publication number: 20200152377Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Applicant: STMicroelectroics S.r.l.Inventors: Vincenzo PALUMBO, Gabriella GHIDINI, Enzo CAROLLO, Fabrizio Fausto Renzo TOIA
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Patent number: 10541079Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: GrantFiled: February 5, 2019Date of Patent: January 21, 2020Assignee: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Fausto Renzo Toia
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Publication number: 20190172631Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: ApplicationFiled: February 5, 2019Publication date: June 6, 2019Applicant: STMicroelectronics S.r.l.Inventors: Vincenzo PALUMBO, Gabriella GHIDINI, Enzo CAROLLO, Fabrizio Fausto Renzo TOIA
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Patent number: 10236115Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: GrantFiled: June 8, 2015Date of Patent: March 19, 2019Assignee: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Fausto Renzo Toia
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Publication number: 20150364249Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: ApplicationFiled: June 8, 2015Publication date: December 17, 2015Applicant: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Toia
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Publication number: 20030015753Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor.Type: ApplicationFiled: January 14, 2002Publication date: January 23, 2003Inventors: Cesare Clementi, Gabriella Ghidini, Carlo Riva
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Publication number: 20020158285Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.Type: ApplicationFiled: June 6, 2002Publication date: October 31, 2002Applicant: STMicroelectronics S.r.l.Inventors: Cesare Clementi, Gabriella Ghidini, Mauro Alessandri
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Patent number: 6448138Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.Type: GrantFiled: April 13, 2000Date of Patent: September 10, 2002Assignee: STMicroelectronics S.r.l.Inventors: Cesare Clementi, Gabriella Ghidini, Mauro Alessandri
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Publication number: 20020000636Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor.Type: ApplicationFiled: July 28, 1998Publication date: January 3, 2002Inventors: CESARE CLEMENTI, GABRIELLA GHIDINI, CARLO RIVA
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Patent number: 6248630Abstract: A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.Type: GrantFiled: April 27, 1999Date of Patent: June 19, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Cesare Clementi, Gabriella Ghidini, Carlo Riva
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Patent number: 6114203Abstract: The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms of resistance to degradation due to the passage of charges through it during the operation of the memory, the method provides for a step for the high-temperature nitriding of the oxide. According to a variant, the nitrided oxide formed on the areas intended for the components of the peripheral circuits is removed and then formed again by a similar thermal oxidation treatment followed by high-temperature nitriding.Type: GrantFiled: May 10, 1996Date of Patent: September 5, 2000Assignee: STMicroelectronics S.r.l.Inventors: Gabriella Ghidini, Cesare Clementi
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Patent number: 6004847Abstract: A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.Type: GrantFiled: June 20, 1996Date of Patent: December 21, 1999Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Cesare Clementi, Gabriella Ghidini, Carlo Riva
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Patent number: 5856221Abstract: A process or forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor.Type: GrantFiled: June 20, 1996Date of Patent: January 5, 1999Inventors: Cesare Clementi, Gabriella Ghidini, Carlo Riva
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Patent number: 5600166Abstract: The use of an O--N--RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O--N--O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling.Type: GrantFiled: June 1, 1995Date of Patent: February 4, 1997Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Cesare Clementi, Gabriella Ghidini, Marina Tosi
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Patent number: 5422291Abstract: The use of an O--N--RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O--N--O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling.Type: GrantFiled: May 26, 1993Date of Patent: June 6, 1995Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Cesare Clementi, Gabriella Ghidini, Marina Tosi
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Patent number: 4808261Abstract: The process calls for covering of the dielectric with a thin additional layer of polysilicon which has the function of protecting the dielectric from any defects which would otherwise be introduced from the subsequent masking.Type: GrantFiled: April 20, 1987Date of Patent: February 28, 1989Assignee: SGS Microelettronica S.p.A.Inventors: Gabriella Ghidini, Giuseppe Crisenza