Abstract: Imprint lithography templates having leading and trailing edge borders are provided that achieve zero-gap imprinting between adjacent fields with full-feature height features provided in the pattern exclusion zones (PEZ) located between such fields. The leading edge borders include dummy features, e.g., elongated features directionally oriented parallel to the mesa edge, while the trailing edge border includes a recess extending to the mesa edges. When used in a step-and-repeat process, the trailing edge border overlaps edge portions of an adjacent imprinted field that were previously patterned by the leading edge border of the template, producing full-feature height features in the pattern exclusion zones between such fields, and avoiding gaps or open areas between such fields that otherwise lead to non-uniformity of downstream processes such as etch processes and CMP.

Abstract: Imprint lithography templates having leading and trailing edge borders are provided that achieve zero-gap imprinting between adjacent fields with full-feature height features provided in the pattern exclusion zones (PEZ) located between such fields. The leading edge borders include dummy features, e.g., elongated features directionally oriented parallel to the mesa edge, while the trailing edge border includes a recess extending to the mesa edges. When used in a step-and-repeat process, the trailing edge border overlaps edge portions of an adjacent imprinted field that were previously patterned by the leading edge border of the template, producing full-feature height features in the pattern exclusion zones between such fields, and avoiding gaps or open areas between such fields that otherwise lead to non-uniformity of downstream processes such as etch processes and CMP.

Abstract: The present invention provides, in one aspect, a method of testing an electrical breakdown characteristic of a dielectric in a microelectronic device. This method includes determining a first dielectric breakdown voltage distribution of a first test sample by using a first voltage ramp rate, determining a second dielectric breakdown voltage distribution of a second test sample by using a second voltage ramp rate and determining a spacing distribution between conductive lines in the first and second test samples based on a field acceleration factor associated with the dielectrics of the first and second test samples, the first and second voltage ramp rates, and a difference between the first and second breakdown voltage distributions. This spacing distribution is used to determine corrected electric breakdown fields based on a measured breakdown voltage of a test sample, to improve microelectronic-device screening for interconnect dielectric reliability.