Abstract: A circuit for protecting an input MOS FET (Q1) from electrostatic discharge pulses includes a plurality of diodes (D112a through D112f) coupled to the bonding pad (102) of an integrated circuit via a plurality of resistors (R110a through R110f). The resistors prevent excessive current from flowing through and hence damaging any of the diodes. The diodes possess a unique shape which maximizes the perimeter to surface area ratio and therefore permits more efficient energy dissipation along the periphery of the diodes. The diodes are adapted to break down in response to an excessive voltage at the bonding pad and therefor protect the gate structure of the input transistor. Also included in the circuit is a protective bipolar transistor (Q2) having a collector coupled to the bonding pad, an emitter coupled to ground and a base resistively coupled to ground.