Abstract: An image is compressed by selectively performing at least one of palettization and interframe coding on certain regions of the image. The regions are adaptively determined.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. A linear error correction block code such as a Reed-Solomon code forms codewords having a plurality of symbols. In almost all cases, a corrected codeword is formed by error correction decoding a read codeword in a standard first decoder arranged to reliably identify and correct up to a predetermined number of failed symbols, or else determine an unrecoverable error. Error correction decoding of the read codeword is then attempted in a stronger second decoder, ideally being a maximum likelihood decoder arranged to form one or more closest corrected codewords.

Abstract: A system for memory word error correction that enables correction of burst errors in memory words. The system is based on an adaptation of two-error correction BCH code which yields burst error correction without increasing the number of error correction bits in the memory words over prior two-error BCH code error correction schemes. The adaptation of two-error correction BCH code when combined with additional techniques for detecting columns of burst errors enables the correction of burst errors and additional random bit errors in memory words.

Abstract: A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. Since currently available MRAM devices are subject to physical failures, data storage arrangements are described to minimise the affect of those failures on the stored ECC encoded data, including storing all bits of each symbol in storage cells 16 in one row 12 (FIG. 3), or in at least two rows 12 but using storage cells 16 in the same columns 14 (FIG. 4). Sets of bits taken from each row 12 are allocated to different codewords 204 (FIG. 5) and the order of allocation can be rotated (FIG. 6). A second level of error checking can be applied by adding a parity bit 226 to each symbol 206 (FIG. 7).

Abstract: A random number generator that generates random numbers based on measurements of one or more environmental quantities. The random number generator includes a first sensor for generating a first sequence of digital values representing measurements of a first environmental quantity at successive times. A first compressor that provides a first sequence of compressed values having a lower internal correlation than the values of the first sequence of digital values compresses the sequence of digital values. The random number generator generates an output random number via a circuit for generating a random number from an input sequence of digital values, the input sequence being a function of one of the first sequence of compressed values. The circuit may utilize a hash function to provide further security. In addition, the circuit includes a blocking circuit for preventing the generator from outputting a random number if the input sequences fail a predetermined test.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, a set of test cells 160 in a test row 120 are used to predict failures 163 amongst a set of cells of interest storing a block of ECC encoded data. Erasure information is formed from these predictions which identifies potentially unreliable symbols 206 in the block of ECC encoded data, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columns 14 of an array of storage cells 16 which are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the MRAM device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data. The test comprises identifying failed storage cells where the failures will be visible in use for the generation of erasure information used in ECC decoding, suitably by comparing parametric values obtained from the storage cells against one or more failure ranges, and includes performing a write-read-compare operation with test data to identify failed storage cells which will be hidden for the generation of erasure information in use. A failure count is formed based on both the visible failures and the hidden failures, to determine that the set of storage cells is suitable for storing ECC encoded data. Here, the failure count is weighted, with hidden failures having a greater weighting than visible failures.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A method of decoding an embedded bitstream includes the steps of reading encoded subsequences in the bitstream as ordered, decoding at least some of the ordered subsequences, and combining the subsequences to obtain reconstructed data. The encoded subsequences are read in order of decreasing expected distortion reduction per expected bit of description.

Abstract: A security system based on a tamper resistant badge that becomes deactivated if the badge is removed from the person authorized to wear the badge. The badge has a volatile memory for storing the security clearance information associated with the wearer and a processor having sufficient power to perform encrypted communications. The badge also has an attachment sensor that resets the security clearance information if the badge is removed from the wearer. A secure data processing system utilizing the badges includes an administrative computer, A, and a client computer, C. Computer A has an identity verification system for authenticating the identity of individuals having badges and loading the clearance information into the volatile memory after the badge is attached to the wearer. The C computers access the information in the badge's volatile memory to provide access to the wearer at the access level specified in the volatile memory.

Abstract: A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format.

Abstract: The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address difference. The prefetch engine builds a data structure to represent address differences and weights them according to the accumulated stall time produced by the cache misses given that the corresponding address is not prefetched.

Abstract: A method of generating an embedded bitstream from quantized Wavelet transform coefficients includes the steps of separating the quantized coefficient bit-planes into a plurality of subsequences, ordering the subsequences according to decreasing expected distortion reduction per expected bit of description, encoding the subsequences, and appending the encoded subsequences to the bitstream as ordered. The subsequences may be ordered according to a priori assumptions about the expected distortion reduction per expected bit of description. The subsequences may be coded by adaptive run length coding such as adaptive elementary Golomb coding.

Abstract: A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format.

Abstract: In elliptic curve processing systems, information is typically processed to yield elliptic curve data points, with X and Y coordinates each represented by N bits, N typically being 160 or more. Valid Y coordinates must satisfy a quadratic equation for any given X coordinate, such that any Y data may be represented by its corresponding X coordinate and a single additional byte or bit. In accordance with this disclosure, a vector t is chosen for which the dot product between t and any X coordinate is equal to a constant. The vector t is used in a compression mode of the preferred embodiment to select a bit position in X coordinate data with the X bit at that location being discarded and the Y coordinate information being stored in its place. As a result, an extra byte of data is not needed and any elliptic curve data point may be represented by N bits only.

Abstract: A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format.

Abstract: An apparatus and method are shown for multiplying vectors of length n in a finite field. A first vector is circularly shifted in a first shift register under control of a shift signal. A second vector is circularly shifted in a second shift register also under control of the shift signal. An accumulated result vector is circularly shifted in a third shift register under control of the shift signal. Elements of the second vector are logically combined according to a tensor of the multiplication operation to obtain an intermediate result which is combined with the elements of the accumulated result vector to obtain a combination result vector. However, the combination result vector is only loaded into the third shift register when a logic ‘1’ value is present in a first position of the first shift register.

Abstract: An image compression system having a causal, context-based, single-pass adaptive filter encoder that encodes pixel values using multiple context-based threshold values. In the general case, the threshold value is a function of the context of a pixel being encoded. In one specific embodiment one threshold value is used in non-run mode contexts and another threshold value is used in run mode contexts. A single threshold decompressor may decode images encoded using the multi-threshold encoder of the invention. Other systems and methods are disclosed.

Abstract: A lossless image compression encoder/decoder system having a context determination circuit and a code table generator. The image compressor uses the context of a pixel to be encoded to predict the value of the pixel and determines a prediction error. The image compressor contains a context quantizer that quantizes the context of pixels. The image compressor counts the error values for each quantized context and uses these counts to generate context-specific coding tables for each quantized context. As it encodes a particular pixel, the encoder looks up the prediction error in the context-specific coding table for the context of the pixel and encodes that value. To decompress an image, the decompressor determines and quantizes the context of each pixel being decoded. The decompressor uses the same pixels as the compressor to determine the context. The decompressor retrieves from the context-specific coding table the error value corresponding to the coded pixel.