Patents by Inventor Gael Gautier
Gael Gautier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047601Abstract: A device for measuring a particle beam, includes front and rear faces, a first central portion including a device for forming a space charge region through which a particle beam to be measured passes, charge carriers of a first and second type being generated by the beam when the latter passes through the space charge region, a second peripheral portion including a device for collecting at least one type of charge carrier from the first or second type of charge carriers generated in the space charge region, the central portion having a maximum thickness less than or equal to that of the peripheral portion, the peripheral portion surrounding the central portion such that a particle beam can pass through the central portion without passing through the peripheral portion. The device includes, in a region of the central portion leading to the rear face, a layer of a porous material.Type: ApplicationFiled: December 22, 2021Publication date: February 8, 2024Inventors: Gaël GAUTIER, Wilfried VERVISCH, Damien VALENTE
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Patent number: 10068999Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.Type: GrantFiled: April 29, 2016Date of Patent: September 4, 2018Assignees: STMICROELECTRONICS (TOURS) SAS, UNIVERSITE FRANCOIS RABELAISInventors: Samuel Menard, Gael Gautier
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Patent number: 9780188Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.Type: GrantFiled: November 17, 2016Date of Patent: October 3, 2017Assignees: STMicroelectronics (Tours) SAS, Universite Francois RabelaisInventors: Samuel Menard, Gael Gautier
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Publication number: 20170069733Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Applicants: STMicroelectronics (Tours) SAS, Universite Francois RabelaisInventors: Samuel Menard, Gael Gautier
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Patent number: 9530875Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.Type: GrantFiled: January 7, 2016Date of Patent: December 27, 2016Assignees: STMicroelectronics (Tours) SAS, Universite Francois RabelaisInventors: Samuel Menard, Gael Gautier
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Patent number: 9437722Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.Type: GrantFiled: October 9, 2014Date of Patent: September 6, 2016Assignees: STMicroelectronics (Tours) SAS, Universite Francois RabelaisInventors: Samuel Menard, Gael Gautier
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Publication number: 20160247904Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.Type: ApplicationFiled: April 29, 2016Publication date: August 25, 2016Inventors: SAMUEL MENARD, Gael Gautier
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Patent number: 9343557Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.Type: GrantFiled: February 7, 2013Date of Patent: May 17, 2016Assignees: STMICROELECTRONICS (TOURS) SAS, UNIVERSITE FRANCOIS RABELAISInventors: Samuel Menard, Gaël Gautier
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Publication number: 20160118485Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.Type: ApplicationFiled: January 7, 2016Publication date: April 28, 2016Applicants: STMicroelectronics (Tours) SAS, Universite Francois RabelaisInventors: Samuel Menard, Gael Gautier
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Publication number: 20150108537Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.Type: ApplicationFiled: October 9, 2014Publication date: April 23, 2015Applicants: STMicroelectronics (Tours) SAS, Universite Francois RabelaisInventors: Samuel Menard, Gael Gautier
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Patent number: 8994065Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.Type: GrantFiled: May 23, 2013Date of Patent: March 31, 2015Assignees: STMicroelectronics (Tours) SAS, Universite Francois RabelaisInventors: Samuel Menard, Gaël Gautier
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Patent number: 8901601Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.Type: GrantFiled: February 22, 2013Date of Patent: December 2, 2014Assignees: STMicroelectronics (Tours) SAS, Universite Francois Rabelais UFR Sciences et TechniquesInventors: Samuel Menard, Yannick Hague, Gaël Gautier
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Publication number: 20140217462Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicants: Universite Francois Rabelais, STMicroelectronics (Tours) SASInventors: Samuel Menard, Gaël Gautier
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Publication number: 20130320395Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.Type: ApplicationFiled: May 23, 2013Publication date: December 5, 2013Applicants: Universite Francois Rabelais, STMicroelectronics (Tours) SASInventors: Samuel Menard, Gaël Gautier
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Publication number: 20130228822Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.Type: ApplicationFiled: February 22, 2013Publication date: September 5, 2013Applicants: Universite Francois Rabelais UFR Sciences et Techniques, STMicroelectronics (Tours) SASInventors: Samuel Menard, Yannick Hague, Gaël Gautier
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Publication number: 20110053053Abstract: A porous silicon wafer including, on its upper surface side, multiple recesses, this upper surface being coated with a porous silicon layer having pores smaller than those of the wafer bulk.Type: ApplicationFiled: September 18, 2008Publication date: March 3, 2011Applicant: STMicroelectronics S.A.Inventors: Sébastien Desplobain, Gaël Gautier