Patents by Inventor Gael Paul
Gael Paul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11562050Abstract: An integrated circuit includes: one or more protected circuits; a license control circuit configured to request, from a license issuer, a license for activating the one or more protected circuits, the license request having a seed value; and a cryptographic circuit configured to verify the authenticity of a license received from the license issuer based on the seed value, wherein the license control circuit is configured to impose a validity limit on the received license, and to request a new license from the license issuer before the validity limit of the received license.Type: GrantFiled: December 7, 2018Date of Patent: January 24, 2023Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, Université de Montpellier, ALGODONEInventors: Lionel Torres, Jérôme Rampon, Gaël Paul
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Patent number: 11023621Abstract: The invention relates to a license-verification circuit for selectively activating one or more protected circuits (206) of a device (102) the license-verification circuit being capable of: deducing a device key from an identifier associated with the device (102); receiving a first license; decrypting the first license using the device key in order to extract a first verification code activating a first protected circuit by loading an activation code in an activation log (212) associated with the first protected circuit on the basis of a verification of the first verification code.Type: GrantFiled: July 6, 2016Date of Patent: June 1, 2021Assignees: Universite de Montpellier, Centre National de la Recherche ScientifiqueInventors: Lionel Torres, Jérôme Rampon, Gaël Paul
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Publication number: 20200372128Abstract: An integrated circuit includes: one or more protected circuits; a license control circuit configured to request, from a license issuer, a license for activating the one or more protected circuits, the license request having a seed value; and a cryptographic circuit configured to verify the authenticity of a license received from the license issuer based on the seed value, wherein the license control circuit is configured to impose a validity limit on the received license, and to request a new license from the license issuer before the validity limit of the received license.Type: ApplicationFiled: December 7, 2018Publication date: November 26, 2020Inventors: Lionel TORRES, Jérôme RAMPON, Gaël PAUL
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Patent number: 10296689Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.Type: GrantFiled: July 2, 2014Date of Patent: May 21, 2019Assignee: Synopsys, Inc.Inventors: Smita Bakshi, Kenneth S. McElvain, Gael Paul
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Publication number: 20180196965Abstract: The invention relates to a license-verification circuit for selectively activating one or more protected circuits (206) of a device (102) the license-verification circuit being capable of: deducing a device key from an identifier associated with the device (102); receiving a first license; decrypting the first license using the device key in order to extract a first verification code activating a first protected circuit by loading an activation code in an activation log (212) associated with the first protected circuit on the basis of a verification of the first verification code.Type: ApplicationFiled: July 6, 2016Publication date: July 12, 2018Inventors: Lionel TORRES, Jérôme RAMPON, Gaël PAUL
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Publication number: 20160188774Abstract: A method implemented on a data processing system for circuit design is described. The method comprises identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via nets, and determining whether timing of an element of a particular first portion is sensitive to degradation of a signal from a net associated with the particular first portion. In one embodiment, the method further comprises reporting the determination.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Inventors: Saurabh Adya, Kenneth S. McElvain, Gael Paul
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Patent number: 9280632Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm.Type: GrantFiled: November 2, 2012Date of Patent: March 8, 2016Assignee: Synopsys, Inc.Inventors: Saurabh Adya, Kenneth S. McElvain, Gael Paul
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Publication number: 20150012898Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.Type: ApplicationFiled: July 2, 2014Publication date: January 8, 2015Inventors: Smita Bakshi, Kenneth S. McElvain, Gael Paul
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Patent number: 8661378Abstract: Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed.Type: GrantFiled: September 30, 2009Date of Patent: February 25, 2014Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Gael Paul, Raymond Nijssen, Marcel Van der Goot, Clinton W. Kelly, Virantha Ekanayake
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Patent number: 8443315Abstract: Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.Type: GrantFiled: March 22, 2012Date of Patent: May 14, 2013Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul
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Publication number: 20130061195Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm.Type: ApplicationFiled: November 2, 2012Publication date: March 7, 2013Inventors: Saurabh Adya, Kenneth S. McElvain, Gael Paul
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Patent number: 8307315Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying one or more first portions (e.g., islands) of a design of a circuit, where each of the one or more first portions contains a set of elements interconnected via timing critical nets; and reporting inter-dependency between portions of the circuit in view of the one or more first portions. In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying a first portion (e.g., island) of a design of a circuit, the first portion containing a set of elements interconnected via timing critical nets; and performing a synthesis transformation of the first portion to isolate timing dependency of the first portion on a non-critical net connected to an element of the first portion.Type: GrantFiled: January 30, 2009Date of Patent: November 6, 2012Assignee: Synopsys, Inc.Inventors: Saurabh Adya, Kenneth S. McElvain, Gael Paul
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Patent number: 8301933Abstract: Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.Type: GrantFiled: September 14, 2009Date of Patent: October 30, 2012Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul, Raymond Nijssen, Marcel Van der Goot
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Patent number: 8234607Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output.Type: GrantFiled: September 15, 2009Date of Patent: July 31, 2012Assignee: Achronix Semiconductor CorporationInventors: Virantha Ekanayake, Clinton W. Kelly, Rajit Manohar, Christopher LaFrieda, Gael Paul, Raymond Nijssen, Marcel Van der Goot
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Publication number: 20120180012Abstract: Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.Type: ApplicationFiled: March 22, 2012Publication date: July 12, 2012Inventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul
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Patent number: 8161435Abstract: Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.Type: GrantFiled: July 20, 2009Date of Patent: April 17, 2012Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul
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Publication number: 20120089956Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.Type: ApplicationFiled: December 19, 2011Publication date: April 12, 2012Inventors: Smita Bakshi, Kenneth S. McElvain, Gael Paul
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Patent number: 8104004Abstract: Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to create a modified cyclic structure, wherein the additional state holding elements or initial tokens have substantially identical functionality to the original state holding elements. Other activities may include coupling additional functional logic elements to output nodes of the modified cyclic structure, wherein the additional functional logic elements have substantially identical functionality to the original functional logic elements. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: February 13, 2008Date of Patent: January 24, 2012Assignee: Achronix Semiconductor CorporationInventors: Gael Paul, Denny Scharf, Rajit Manohar
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Patent number: 8082138Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.Type: GrantFiled: March 13, 2003Date of Patent: December 20, 2011Assignee: Synopsys, Inc.Inventors: Smita Bakshi, Kenneth S. McElvain, Gael Paul
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Patent number: 7982502Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.Type: GrantFiled: September 15, 2009Date of Patent: July 19, 2011Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Gael Paul, Marcel Van der Goot, Raymond Nijssen, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake