Patents by Inventor Gaetano Bazzano

Gaetano Bazzano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8525253
    Abstract: A semiconductor structure including a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer set in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer set in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: September 3, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Monica Micciche′, Antonio Giuseppe Grimaldi, Gaetano Bazzano, Nicolò Frazzetto
  • Publication number: 20110095358
    Abstract: A semiconductor structure including a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer set in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer set in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer.
    Type: Application
    Filed: October 27, 2010
    Publication date: April 28, 2011
    Applicant: STMicrolectronics S.r.l.
    Inventors: Monica Micciche', Antonio Giuseppe Grimaldi, Gaetano Bazzano, Nicolò Frazzetto
  • Patent number: 7788611
    Abstract: A method models the electrical characteristics of wide-channel transistors, such as power transistors, by generating a lumped-element distributed circuit model. More specifically, the active area of the transistor is organized in elementary transistor cells, which are substituted by active lumped elements. Similarly the passive area of the transistor is organized in elementary strip-lines, which are substituted by passive lumped elements. Preferably, the parameters of the lumped elements are extracted automatically from layout information, such as path dimensions, and technological data, such as sheet resistance of the metal layers, sheet resistance of the polysilicon layers and oxide thickness.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: August 31, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Tonio Gaetano Biondi, Giuseppe Greco, Salvatore Rinaudo, Gaetano Bazzano
  • Patent number: 7715159
    Abstract: An electro-static discharge protection circuit including: a first input terminal and a second input terminal; a first output terminal coupled to the first input terminal, and a second output terminal coupled to the second input terminal; a first circuit branch connected between the first input terminal and the second input terminal, said first circuit branch including at least one first Zener diode having a cathode terminal and an anode terminal; a second circuit branch connected between the first output terminal and the second output terminal, wherein the first circuit branch comprises a load element coupled between the second input terminal and the anode terminal of the at least one first Zener diode; the second circuit branch includes a first transistor having a control terminal adapted to receive a transistor control voltage, the first transistor being coupled to the load element so as to receive from the load element the transistor control voltage.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: May 11, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gaetano Bazzano, Giuseppe Consentino, Antonio Grimaldi, Monica Micciché
  • Patent number: 7569883
    Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: August 4, 2009
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri, Antonio Giuseppe Grimaldi, Gaetano Bazzano
  • Publication number: 20080022246
    Abstract: A method models the electrical characteristics of wide-channel transistors, such as power transistors, by generating a lumped-element distributed circuit model. More specifically, the active area of the transistor is organized in elementary transistor cells, which are substituted by active lumped elements. Similarly the passive area of the transistor is organized in elementary strip-lines, which are substituted by passive lumped elements. Preferably, the parameters of the lumped elements are extracted automatically from layout information, such as path dimensions, and technological data, such as sheet resistance of the metal layers, sheet resistance of the polysilicon layers and oxide thickness.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 24, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Tonio Biondi, Giuseppe Greco, Salvatore Rinaudo, Gaetano Bazzano
  • Publication number: 20080013231
    Abstract: An electro-static discharge protection circuit including: a first input terminal and a second input terminal; a first output terminal coupled to the first input terminal, and a second output terminal coupled to the second input terminal; a first circuit branch connected between the first input terminal and the second input terminal, said first circuit branch including at least one first Zener diode having a cathode terminal and an anode terminal; a second circuit branch connected between the first output terminal and the second output terminal, wherein the first circuit branch comprises a load element coupled between the second input terminal and the anode terminal of the at least one first Zener diode; the second circuit branch includes a first transistor having a control terminal adapted to receive a transistor control voltage, the first transistor being coupled to the load element so as to receive from the load element the transistor control voltage.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 17, 2008
    Applicant: STMicroelectronics S.r.l.
    Inventors: Gaetano Bazzano, Giuseppe Consentino, Antonio Grimaldi, Monica Micciche
  • Publication number: 20060220121
    Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.
    Type: Application
    Filed: November 21, 2005
    Publication date: October 5, 2006
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri, Antonio Grimaldi, Gaetano Bazzano