Abstract: In one embodiment a sensor calibration system includes a robotic platform able to navigate to sensors distributed throughout an environment. The sensors may measure, for example, acoustic levels, temperature, luminance, or humidity. The robotic platform is equipped with at least one set of calibrated sensors and is capable of maneuvering around the environment to respective positions adjacent to the sensors to perform on site calibration. Such proximity also permits recharging power supplies of sensors and download/upload of information to and from the sensor.

Abstract: In one embodiment a software control system supports sensor control services, robotic control services, and database management services on at least two independent software systems. Available services are registerable between one or more services using communication between the services via messages not guaranteed to be delivered.

Abstract: In one embodiment a sensor calibration system includes a robotic platform able to navigate to sensors distributed throughout an environment. The sensors may measure, for example, acoustic levels, temperature, luminance, or humidity. The robotic platform is equipped with at least one set of calibrated sensors and is capable of maneuvering around the environment to respective positions adjacent to the sensors to perform on site calibration. Such proximity also permits recharging power supplies of sensors and download/upload of information to and from the sensor.

Abstract: A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.

Abstract: A field programmable gate array (FPGA) comprising routing and logic blocks (RLBs) and segmented routing channels is disclosed. Each RLB is configurable to perform both logic functions and routing functions. A plurality of forwardly propagating RLBs (FPRLBs) and a plurality of backwardly propagating RLBs (BPRLBs) intermesh with one another to form a two-dimensional checkerboard array. Each column of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. Similarly, each row of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. The FPRLBs forwardly propagate signals and the BPRLBs backwardly propagate signals. Each FPRLB may receive a plurality of input signals from a plurality of FPRLBs in the preceding leftward column. Moreover, each FPRLB may output a plurality of output signals to a plurality of FPRLBs in the next rightward column.

Abstract: A data and clock recovery system is provided in the signal handling receiver (SHRx) stage of an integrated MOS circuit data communication controller to provide accurate sampling of an incoming data packet for recovery of the data and data clock, regardless of differences in the electrical and environmentally affected characteristics of the circuit elements comprising the integrated MOS/VLSI semiconductor chip.

Abstract: A self-calibrated clock and timing signal generator provides reliable and continuous arbitrary digital waveforms of preselectable edge resolution. The generator comprises a multistage means to produce a time delayed signal of preselectable edge resolution and having a plurality of outputs or taps between a plurality of series connected delay stages comprising the multistage means. The delay per stage is substantially identical so that the selection of any one of the outputs is representative of a predetermined amount of delay provided to an input signal to the multistage means. Calibrating means is integrally included to develop a control signal which is coupled to each of the stages of the multistage means to continuously maintain the predetermined amount of delay per stage. In the embodiment described, the calibrating means takes the form of an automatic frequency control (AFC) loop wherein the frequency of a voltage controlled oscillator (VCO) is regulated to be equal to that of a reference frequency.