Patents by Inventor Gaetano Maria Walter Petrina
Gaetano Maria Walter Petrina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804769Abstract: In some examples, an apparatus includes a driver having a driver output, a capacitor having a first plate and a second plate, the first plate coupled to the driver output, and a transistor having a transistor gate, a transistor source, and a transistor drain. The apparatus also includes a first switch coupled between the second plate and the transistor gate, a second switch coupled between the second plate and the transistor drain, and a third switch coupled between the transistor gate and the transistor drain.Type: GrantFiled: December 30, 2020Date of Patent: October 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eduardas Jodka, Gaetano Maria Walter Petrina, Manuel Wiersch
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Publication number: 20230336167Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Inventors: Gaetano Maria Walter Petrina, Michael Lueders, Nicola Rasera
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Patent number: 11728798Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.Type: GrantFiled: December 18, 2019Date of Patent: August 15, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gaetano Maria Walter Petrina, Michael Lueders, Nicola Rasera
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Publication number: 20220209654Abstract: In some examples, an apparatus includes a driver having a driver output, a capacitor having a first plate and a second plate, the first plate coupled to the driver output, and a transistor having a transistor gate, a transistor source, and a transistor drain. The apparatus also includes a first switch coupled between the second plate and the transistor gate, a second switch coupled between the second plate and the transistor drain, and a third switch coupled between the transistor gate and the transistor drain.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Eduardas JODKA, Gaetano Maria Walter PETRINA, Manuel WIERSCH
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Patent number: 11258363Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.Type: GrantFiled: December 12, 2019Date of Patent: February 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joerg Kirchner, Stefan Dietrich, Gaetano Maria Walter Petrina
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Publication number: 20210184575Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.Type: ApplicationFiled: December 12, 2019Publication date: June 17, 2021Inventors: Joerg KIRCHNER, Stefan DIETRICH, Gaetano Maria Walter PETRINA
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Publication number: 20210126538Abstract: A converter having an input adapted to be connected to an input voltage and an output adapted to supply an output voltage, the converter comprising: a high-side switch having a first current terminal, a second current terminal and a first control terminal, the first current terminal is coupled to the input voltage and the second current terminal is coupled to a switching node; a high-side driver circuit having an input, a first supply input, a second supply input and an output coupled to the first control terminal, the second supply input is coupled to the switching node; a bootstrap capacitor having a first terminal and a second terminal, the first terminal coupled to the first supply input and the second terminal coupled to the second supply input; a switch having a first terminal and a second terminal, the first terminal of the switch is coupled to the first terminal of the bootstrap capacitor and the second terminal of the switch is connected to a supply voltage (VDD volts above ground).Type: ApplicationFiled: September 30, 2020Publication date: April 29, 2021Inventors: Emiliano Alejandro Puia, Gaetano Maria Walter Petrina, Puneet Sareen
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Publication number: 20200358357Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.Type: ApplicationFiled: May 6, 2019Publication date: November 12, 2020Inventors: Gaetano Maria Walter Petrina, Joerg Kirchner
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Patent number: 10819237Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.Type: GrantFiled: May 6, 2019Date of Patent: October 27, 2020Assignee: Texas Instruments IncorporatedInventors: Gaetano Maria Walter Petrina, Joerg Kirchner
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Publication number: 20200127652Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Gaetano Maria Walter Petrina, Michael Lueders, Nicola Rasera
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Patent number: 10547296Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.Type: GrantFiled: May 30, 2018Date of Patent: January 28, 2020Assignee: Texas Instruments IncorporatedInventors: Gaetano Maria Walter Petrina, Michael Lueders, Nicola Rasera
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Publication number: 20180351539Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.Type: ApplicationFiled: May 30, 2018Publication date: December 6, 2018Inventors: Gaetano Maria Walter Petrina, Michael Lueders, Nicola Rasera
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Patent number: 9444338Abstract: Various embodiments of the invention provide for a double measurement technique to enable auto-calibration of a switching regulator. In certain embodiments, calibration is performed using a digital conversion circuit that adjusts an internal slope of an on-time generator by adjusting the peak value of a ramp to a desired peak voltage value. Auto-calibration allows for an optimal dynamic response across the entire switching frequency range of the switching regulator even in noisy environments.Type: GrantFiled: April 16, 2013Date of Patent: September 13, 2016Assignee: Maxim Integrated Products, Inc.Inventors: Salvatore Giovanni Pastorina, Antonio Magazzu′, Antonio Panebianco, Gaetano Maria Walter Petrina