Abstract: A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

Abstract: A Logic Built-In Self-Test (LBIST) domain of an integrated circuit is divided into partitions that in turn are subdivided into sub-partitions. Each sub-partition has an associated clock gating logic circuit that enables or inhibits the clock signal supplied to scan chains within the sub-partition. A user-defined number of sub-partitions, which can be specified on the basis of silicon results and power requirements of the integrated circuit, may be activated at any one time during a portion of an LBIST execution, which reduces toggling of concurrent scan chains, resulting in a reduction of energy consumption during testing, and reduces voltage droop due to inertia of power management control modules at the start of an LBIST test.