Abstract: Disclosed is a facial recognition system/method, utilizing modules to perform the following routine: extracting a feature descriptor from a detected feature point of a detected face in an input image frame; and matching the extracted feature descriptor with at least one of a pre-stored facial image that is index-mapped, comprising at least a first and second round of matching, wherein the second round of matching only selects the index-mapped facial images that matched above a pre-defined threshold from the first round of matching. Optionally, the above described steps may be coupled to a Point-of-Recognition (POR) provisioning, enabling an on-demand gate-keeping and/or payment processing for an end-user at an event/venue entry or point-of-sale.

Abstract: A method includes a server computer receiving data relating to a plurality of delivery orders from service providers to end users, and data relating to a plurality of delivery orders from end users to service providers. The server computer determines a plurality of routes corresponding to the plurality of delivery orders. The server computer can then determine a set of optimal route plans by combining delivery order routes. The server computer can then receive acceptances from a plurality of transporters that will execute the set of optimal route plans. The server computer can then facilitate execution of the optimal route plans.

Abstract: A method includes providing, by server computer to a service provider, an onboarding interface for onboarding a service provider to accept returns initiated by end users and from a plurality of available transporters, and then receiving, by the server computer, selections from the service provider regarding different options for processing returns via the onboarding interface. The server computer can receive a plurality of return orders for a plurality of items from a plurality of end users. and process the return orders according to the stored and selected options.

Abstract: A method includes receiving, by a server computer, request from an end user of an item to deliver the item to a service provider. The method includes providing, by the server computer, a retrieval message to a transporter to travel to the end user to retrieve the item and determine if the item is suitable for return to the service provider, and receiving, by the server computer, an item confirmation message from the transporter that the item is suitable for return to the service provider. The method also includes receiving, by the server computer, a delivery confirmation message from the transporter that the item was successfully delivered to the service provider.

Abstract: A reach matrix scheduler circuit for scheduling instructions to be executed in a processor is disclosed. The scheduler circuit includes an N×R matrix wake-up circuit, where ‘N’ is the instruction window size of the scheduler circuit, and ‘R’ is the “reach” within the instruction window of the matrix wake-up circuit, with ‘R’ being less than ‘N’. A grant line associated with each instruction request entry in the N×R matrix wake-up circuit is coupled to ‘R’ other instruction entries among the ‘N’ instruction entries. When a producer instruction in an instruction request entry is ready for issuance, the grant line associated with the instruction request entry is activated so that any other instruction entries coupled to the grant line (i.e., within the “reach” of the instruction request entry) that consume the produced value generated by the producer instruction are “woken-up” and subsequently indicated as ready to be issued.

Abstract: An example method includes, at an electronic device: receiving an indication of a notification; in accordance with receiving the indication of the notification: obtaining one or more data streams from one or more sensors; determining, based on the one or more data streams, whether a user associated with the electronic device is speaking; and in accordance with a determination that the user is not speaking: causing an output associated with the notification to be provided.

Abstract: Embodiments described herein are directed to a microarchitecture modeling tool configured to model and analyze a microarchitecture using a dependency graph. The dependency graph may be generated based on an execution trace of a program and a microarchitecture definition that specifies various features and/or characteristics of the microarchitecture on which the execution trace is based. The dependency graph includes vertices representing different microarchitectural events. The vertices are coupled via edges representing a particular dependency therebetween. The edges are associated with a cost for performing microarchitectural event(s) corresponding to the vertices coupled thereto. The dependency graph also takes into account various policies for structural hazards of the microarchitecture. The microarchitecture modeling tool analyzes the costs associated with each of the edges to determine a design metric of the microarchitecture.

Abstract: Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.

Abstract: Systems, methods, and devices are described coordinating a distributed accelerator. A command that includes instructions for performing a task is received. One or more sub-tasks of the task are determined to generate a set of sub-tasks. For each sub-task of the set of sub-tasks, an accelerator slice of a plurality of accelerator slices of a distributed accelerator is allocated, sub-task instructions for performing the sub-task are determined. Sub-task instructions are transmitted to the allocated accelerator slice for each sub-task. Each allocated accelerator slice is configured to generate a corresponding response indicative of the allocated accelerator slice having completed a respective sub-task. In a further example aspect, corresponding responses are received from each allocated accelerator slice and a coordinated response indicative of the corresponding responses is generated.

Abstract: An example method includes, at an electronic device: receiving an indication of a notification; in accordance with receiving the indication of the notification: obtaining one or more data streams from one or more sensors; determining, based on the one or more data streams, whether a user associated with the electronic device is speaking; and in accordance with a determination that the user is not speaking: causing an output associated with the notification to be provided.

Abstract: Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address.

Abstract: Systems and methods are disclosed for allocating resources to contexts in block-based processor architectures. In one example of the disclosed technology, a processor is configured to spatially allocate resources between multiple contexts being executed by the processor, including caches, functional units, and register files. In a second example of the disclosed technology, a processor is configured to temporally allocate resources between multiple contexts, for example, on a clock cycle basis, including caches, register files, and branch predictors. Each context is guaranteed access to its allocated resources to avoid starvation from contexts competing for resources of the processor. A results buffer can be used for folding larger instruction blocks into portions that can be mapped to smaller-sized instruction windows. The results buffer stores operand results that can be passed to subsequent portions of an instruction block.

Abstract: Systems and processes for providing a virtual assistant service are provided. In accordance with one or more examples, a method includes receiving, from an accessory device communicatively coupled to the first electronic device, a representation of a speech input representing a user request. The method further includes detecting a second electronic device and transmitting, from the first electronic device, a representation of the user request and data associated with the detected second electronic device to a third electronic device. The method further includes receiving, from the third electronic device, a determination of whether a task is to be performed by the second electronic device in accordance with the user request; and in accordance with a determination that a task is to be performed by the second electronic device, requesting the second electronic device to performed the task in accordance with the user request.

Abstract: Systems and methods are disclosed for allocating resources to contexts in block-based processor architectures. In one example of the disclosed technology, a processor is configured to spatially allocate resources between multiple contexts being executed by the processor, including caches, functional units, and register files. In a second example of the disclosed technology, a processor is configured to temporally allocate resources between multiple contexts, for example, on a clock cycle basis, including caches, register files, and branch predictors. Each context is guaranteed access to its allocated resources to avoid starvation from contexts competing for resources of the processor. A results buffer can be used for folding larger instruction blocks into portions that can be mapped to smaller-sized instruction windows. The results buffer stores operand results that can be passed to subsequent portions of an instruction block.

Abstract: Photon generating substrates for light-directed oligonucleotide synthesis are disclosed. Light is generated within a solid-state stack that supports growing oligonucleotides. The light may be generated by microLEDs, a pass-through liquid crystal panel, or an LCoS system. Light passes through a transmissive layer on which growing oligonucleotides are attached. Patterning of the light is controlled by selective activation of the microLEDs or by selective control of the transparency of a liquid crystal layer. Photolabile blocking groups are selectively removed by exposure to patterned light emitted from the photon generating substrate.

Abstract: Systems and processes for operating an intelligent automated assistant are provided. In one example process, a first and second notification are received and, in accordance with determinations that the respective notifications are to be announced to a user, respective first and second spoken outputs are obtained. An announcement schedule is determined based on the respective types of the notifications and the first and second spoken outputs are provided (e.g., audibly announced) according to the announcement schedule.

Abstract: Polymers synthesized by solid-phase synthesis are selectively released from a solid support by reversing the bias of spatially addressable electrodes. Change in the current and voltage direction at one or more of the spatially addressable electrodes changes the ionic environment which triggers cleavage of linkers that leads to release of the attached polymers. The spatially addressable electrodes may be implemented as CMOS inverters embedded in an integrated circuit (IC). The IC may contain an array of many thousands of spatially addressable electrodes. Control circuity may independently reverse the bias on any of the individual electrodes in the array. This provides fine-grained control of which polymers are released from the solid support. Examples of polymers that may be synthesized on this type of array include oligonucleotides and peptides.

Abstract: Systems and processes for providing a virtual assistant service are provided. In accordance with one or more examples, a method includes receiving, from an accessory device communicatively coupled to the first electronic device, a representation of a speech input representing a user request. The method further includes detecting a second electronic device and transmitting, from the first electronic device, a representation of the user request and data associated with the detected second electronic device to a third electronic device. The method further includes receiving, from the third electronic device, a determination of whether a task is to be performed by the second electronic device in accordance with the user request; and in accordance with a determination that a task is to be performed by the second electronic device, requesting the second electronic device to performed the task in accordance with the user request.

Abstract: Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address.

Abstract: Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction.