Patents by Inventor Gage Krieger HILLS

Gage Krieger HILLS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11790141
    Abstract: System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: October 17, 2023
    Assignee: Massachusetts Institute of Technology
    Inventors: Gage Krieger Hills, Max Shulaker
  • Publication number: 20210294959
    Abstract: System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.
    Type: Application
    Filed: June 2, 2021
    Publication date: September 23, 2021
    Inventors: Gage Krieger HILLS, Max SHULAKER
  • Patent number: 11062067
    Abstract: System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 13, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Gage Krieger Hills, Max Shulaker
  • Publication number: 20200082032
    Abstract: System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 12, 2020
    Inventors: Gage Krieger HILLS, Max SHULAKER