Abstract: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector.

Abstract: A computer-implemented method for performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. A step of the coordinate rotation digital computer algorithm is performed. As a result of performing the step, a value of the coordinate rotation digital computer algorithm is reduced. The value is shifted using a physical adder. A set of bits of the physical adder is disabled, wherein the set of bits corresponds to at least one high order zero of the value.

Abstract: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to at least one of a plurality of decoders, wherein each decoder is adapted to recognize the coding scheme represented by one of the bit patterns.