Abstract: A liquid crystal display panel includes an array substrate, a color filter substrate, a plurality of pad structures disposed between the array substrate and the color filter substrate, a display area, and a light transmissive functional area. The pad structures are correspondingly disposed on the display area. The display area includes a predetermined area disposed at a periphery of the light transmissive functional area, and a thickness of each of the pad structures disposed on the predetermined area gradually decreases along a direction from the predetermined area to the light transmissive functional area.

Abstract: The present application provides an array substrate and a liquid crystal display panel. The array substrate includes: a substrate including a display area and a light-transmitting functional area; a buffer layer disposed on the substrate and covering the display area and the light-transmitting functional area; a thin film transistor array layer disposed on the buffer layer, the thin film transistor array layer is provided with an aperture, and the aperture and the light-transmitting functional area are aligned with each other; and a support filling structure disposed in the aperture.

Abstract: The present application provides an array substrate and a liquid crystal display panel. The array substrate includes: a substrate including a display area and a light-transmitting functional area; a buffer layer disposed on the substrate and covering the display area and the light-transmitting functional area; a thin film transistor array layer disposed on the buffer layer, the thin film transistor array layer is provided with an aperture, and the aperture and the light-transmitting functional area are aligned with each other; and a support filling structure disposed in the aperture.

Abstract: A liquid crystal display panel includes an array substrate, a color filter substrate, a plurality of pad structures disposed between the array substrate and the color filter substrate, a display area, and a light transmissive functional area. The pad structures are correspondingly disposed on the display area. The display area includes a predetermined area disposed at a periphery of the light transmissive functional area, and a thickness of each of the pad structures disposed on the predetermined area gradually decreases along a direction from the predetermined area to the light transmissive functional area.

Abstract: A touch array substrate and a touch display panel are provided, including a base substrate, a TFT layer, a flat layer, a metal wiring layer, an insulating layer, a bottom transparent electrode, a passivation layer and a top transparent electrode. The metal wiring layer includes a touch signal line, a dummy wiring and a connection wiring connecting the touch signal line and the dummy wiring. The critical dimension of the connection wiring is smaller than the critical dimensions of the touch signal line and the dummy wiring, or a portion of the connection wiring close to the first via is bent away from the first via, to enlarge the distance between the connection wiring and the first via. The connection wiring is prevented from falling into the first via and contacting the TFT layer, and the top transparent electrode and the bottom transparent electrode are prevented from being directly short-circuited.

Abstract: A liquid crystal display panel and a substrate manufacturing method are provided. The liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. A first protrusion is disposed on a surface of the array substrate away from the liquid crystal layer, a second protrusion is disposed on a surface of the color filter substrate away from the liquid crystal layer, and the first protrusion is opposite to the second protrusion.

Abstract: A liquid crystal display panel and a substrate manufacturing method are provided. The liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. A first protrusion is disposed on a surface of the array substrate away from the liquid crystal layer, a second protrusion is disposed on a surface of the color filter substrate away from the liquid crystal layer, and the first protrusion is opposite to the second protrusion.

Abstract: The present disclosure provides a thin film transistor (TFT) substrate and a manufacturing method thereof. The TFT substrate include a TFT; a flat layer to cover the TFT; an opening hole defined in the flat layer and corresponding to a drain of the TFT; a bottom of the opening hole to retain a part of the flat layer for forming a flat layer sheet; a first metal layer formed on the flat layer; a first insulating layer formed on the first metal; a second metal formed on the first insulating layer and pass through the flat layer sheet for electrically connecting to the drain.

Abstract: A touch array substrate and a touch display panel are provided, including a base substrate, a TFT layer, a flat layer, a metal wiring layer, an insulating layer, a bottom transparent electrode, a passivation layer and a top transparent electrode. The metal wiring layer includes a touch signal line, a dummy wiring and a connection wiring connecting the touch signal line and the dummy wiring. The critical dimension of the connection wiring is smaller than the critical dimensions of the touch signal line and the dummy wiring, or a portion of the connection wiring close to the first via is bent away from the first via, to enlarge the distance between the connection wiring and the first via. The connection wiring is prevented from falling into the first via and contacting the TFT layer, and the top transparent electrode and the bottom transparent electrode are prevented from being directly short-circuited.

Abstract: An antistatic display panel and a manufacturing method thereof are provided. The antistatic display panel includes a display area, a flexible circuit board, a driving chip, and an electrostatic discharge circuit. The driving chip is fixed on a surface of the flexible circuit board and is bound to a lower edge of the display area. A plurality of pins of the driving chip are electrically connected to the electrostatic discharge circuit, and the pins form a closed loop with the electrostatic discharge circuit.

Abstract: The present disclosure provides a thin film transistor (TFT) substrate and a manufacturing method thereof. The TFT substrate include a TFT; a flat layer to cover the TFT; an opening hole defined in the flat layer and corresponding to a drain of the TFT; a bottom of the opening hole to retain a part of the flat layer for forming a flat layer sheet; a first metal layer formed on the flat layer; a first insulating layer formed on the first metal; a second metal formed on the first insulating layer and pass through the flat layer sheet for electrically connecting to the drain.

Abstract: The disclosure relates to a low temperature polycrystalline silicon thin film transistor including: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer; a gate insulation layer formed on the buffer layer and the semiconductor layer; gates formed on the gate insulation layer; a dielectric layer formed on the gate insulation layer and the gates; a passivation layer formed on the dielectric layer; a first contact hole and a second contact hole formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and sources ad drains formed respectively on the first contact hole and the second contact hole; the semiconductor layer being a low temperature poly silicon layer, and a reflective layer and/or an insulation layer disposed between the buffer layer and the semiconductor layer. The disclosure further relates to a manufacturing method for aforementioned thin film transistor.

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.

Abstract: The disclosure relates to a low temperature polycrystalline silicon thin film transistor including: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer; a gate insulation layer formed on the buffer layer and the semiconductor layer; gates formed on the gate insulation layer; a dielectric layer formed on the gate insulation layer and the gates; a passivation layer formed on the dielectric layer; a first contact hole and a second contact hole formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and sources ad drains formed respectively on the first contact hole and the second contact hole; the semiconductor layer being a low temperature poly silicon layer, and a reflective layer and/or an insulation layer disposed between the buffer layer and the semiconductor layer. The disclosure further relates to a manufacturing method for aforementioned thin film transistor.

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystallizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).