Patents by Inventor Gaius Gillman Fountain, Jr.

Gaius Gillman Fountain, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252364
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 15, 2019
    Inventors: Cyprian Emeka UZOH, Laura Wills MIRKARIMI, Guilian GAO, Gaius Gillman FOUNTAIN, JR.
  • Publication number: 20190244899
    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Javier A. DeLaCruz
  • Patent number: 10366962
    Abstract: A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 30, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr.
  • Publication number: 20190181107
    Abstract: Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 13, 2019
    Inventors: Javier A. DELACRUZ, Rajesh KATKAR, Shaowu HUANG, Gaius Gillman FOUNTAIN, JR., Liang WANG, Laura Wills MIRKARIMI
  • Patent number: 10312217
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 4, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Publication number: 20190148222
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Application
    Filed: November 30, 2018
    Publication date: May 16, 2019
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Qin-Yi Tong
  • Patent number: 10269708
    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Javier A. DeLaCruz
  • Publication number: 20190096842
    Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 28, 2019
    Inventors: Gaius Gillman FOUNTAIN, JR., Chandrasekhar MANDALAPU, Cyprian Emeka UZOH, Jeremy Alfred THEIL
  • Patent number: 10147641
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 4, 2018
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Publication number: 20180331066
    Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
    Type: Application
    Filed: April 23, 2018
    Publication date: November 15, 2018
    Inventors: Cyprian Emeka UZOH, Guilian GAO, Laura Wills MIRKARIMI, Gaius Gillman FOUNTAIN, JR.
  • Publication number: 20180331000
    Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.
    Type: Application
    Filed: December 11, 2017
    Publication date: November 15, 2018
    Inventors: Javier A. DELACRUZ, Paul M. ENQUIST, Gaius Gillman FOUNTAIN, JR., Ilyas MOHAMMED
  • Publication number: 20180204798
    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
    Type: Application
    Filed: December 22, 2017
    Publication date: July 19, 2018
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Javier A. DeLaCruz
  • Patent number: 9852988
    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 26, 2017
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Javier A. DeLaCruz
  • Publication number: 20170316971
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Qin-Yi Tong
  • Patent number: 9716033
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 25, 2017
    Assignee: ZIPTRONIX, INC.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Publication number: 20170200711
    Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.
    Type: Application
    Filed: December 22, 2016
    Publication date: July 13, 2017
    Inventors: Cyprian Emeka Uzoh, Paul M. Enquist, Gaius Gillman Fountain, JR.
  • Publication number: 20170179029
    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 22, 2017
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Javier A. DeLaCruz
  • Publication number: 20170170132
    Abstract: A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 15, 2017
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR.
  • Patent number: 9564414
    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: February 7, 2017
    Assignee: ZIPTRONIX, INC.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr.
  • Publication number: 20160322328
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 3, 2016
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, JR., Paul M. Enquist