Abstract: A stacked electronic device is disclosed. The stacked electronic device can comprise a die stack including two or more connected dies, such as a lower die, an upper die, and a middle die between the lower die and the upper die. A plurality of through substrate vias (TSVs) can provide signal transmission to dies of the stack. A power supply path can be configured to provide power to the middle die without passing through the lower die. In some embodiments, external paths can provide power through an upper surface of a die in the stack while signals are supplied through the lower surface.

Abstract: Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and/or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1° C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds.

Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

Abstract: Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes providing a first element having a first bonding surface, providing a second element having a second bonding surface, slightly etching the first bonding surface, treating the first bonding surface with a terminating liquid treatment to terminate the first bonding surface with a terminating species, and directly bonding the first bonding surface to the second bonding surface without the use of an intervening adhesive and without exposing the first bonding surface to plasma.

Abstract: A multi-die electronic apparatus is disclosed. The multi-die electronic apparatus can comprise a first die comprising first communication pads, the first die having a first device surface including first devices, and a first back surface opposite the first device surface. A second die can include second communication pads, the second die having a second device surface including second devices, and a second back surface opposite the first device surface. The first and second dies can be vertically stacked with the second back surface facing the first device surface. At least one of the first communication pads can communicate a non-noise signal capacitively with at least one of the second communication pads.

Abstract: Microelectronic devices having stacked electromagnetic coils are disclosed. In one example, a microelectronic device can include a first semiconductor element and a second semiconductor element disposed on the first semiconductor element. The microelectronic device can also include an electromagnetic coil. A first portion of the electromagnetic coil and a second portion of the electromagnetic coil may be spaced apart by the first semiconductor element. A first conductive via extending through the first semiconductor element may connect the first and second portions of the electromagnetic coil. Methods for forming such microelectronic devices are also disclosed.

Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Abstract: A bonded structure is disclosed. The bonded structure can include a first element that includes a first bonding layer, the first bonding layer that has a first contact pad and a routing trace. The routing trace is formed at the same level as the first contact pad. The bonded structure can include a second element that includes a second bonding layer that has a second contact pad.

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Abstract: A bonding method is disclosed. The method can include directly bonding a first nonconductive bonding material of a semiconductor element to a second nonconductive bonding material of a carrier without an intervening adhesive. The first nonconductive bonding material is disposed on a device portion of the semiconductor element. The second nonconductive bonding material is disposed on a bulk portion of the carrier. A deposited dielectric layer is disposed between the device portion and the bulk portion. The method can include removing the carrier from the semiconductor element by transferring thermal energy to the dielectric layer to induce diffusion of gas out of the dielectric layer.

Abstract: A method of processing a semiconductor element is disclosed. The method can include providing the semiconductor element that has a first nonconductive material. The first nonconductive material is disposed on a device portion of the semiconductor element. The method can include providing a transparent carrier. The method can include providing an intervening structure that has a second nonconductive material, a photolysis layer, and an opaque layer stacked together. The method can include forming a bonded structure such that the second nonconductive material is directly bonded to the first nonconductive material or to the transparent carrier. The intervening structure is disposed between the semiconductor element and the transparent carrier. The method can include decoupling the transparent carrier from the semiconductor element by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers.

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.

Abstract: A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Abstract: A microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion that has a first surface and a second surface opposite the first surface. The microelectronic structure can include a via structure that extends at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface. The microelectronic structure can include a first dielectric barrier layer that is disposed on the first surface of the bulk semiconductor portion and extends to the via structure. The microelectronic structure can include a second dielectric layer that is disposed on the first dielectric barrier layer and extends to the via structure.