Abstract: A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.

Abstract: Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.

Abstract: An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well.

Abstract: Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

Abstract: Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

Abstract: Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.

Abstract: A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state.

Abstract: A method of producing pristine graphene particles through a one-step, gas-phase, catalyst-free detonation of a mixture of one or more carbon-containing compounds hydrocarbon compounds and one or more oxidizing agents is provided. The detonation reaction occurs very quickly and at relatively high temperature, greater than 3000 K, to generate graphene nanosheets that can be recovered from the reaction vessel, such as in the form of an aerosol. The graphene nanosheets may be stacked in single, double, or triple layers, for example, and may have an average particle size of between about 35 to about 250 nm.

Abstract: An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well.

Abstract: A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.

Abstract: System and method for on board digital entertainment, communication and information system for mass transportation medium (static or mobile) is presented. The system consists of server, software algorithm and client devices. Client devices are connected wirelessly to the server and the server is connected to other servers and external medium wirelessly thereby providing seamless connectivity to the client devices to the server and to outside world. A server design is presented with multiple redundancies to provide un-interrupted services. A client design is presented that enables connectivity to a known server and can be manufactured with low cost. A software algorithm is presented that can prioritize among multiple tasks.