Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

Abstract: A semiconductor device according to an embodiment, includes a stacked body, a plurality of first terraces, a second terrace, a plurality of interconnects, a plurality of conductive bodies. The stacked body includes a plurality of electrode layers. The stacked body includes a stairstep portion at an end portion of the stacked body. The plurality of first terraces are provided in the stairstep portion. The second terrace is provided in the stairstep portion. The plurality of interconnects are provided from the second terrace to the plurality of first terraces. The plurality of interconnects contact one of the plurality of electrode layers at the stairstep portion. The plurality of conductive bodies are provided above the second terrace. The plurality of conductive bodies extend in a stacking direction of the stacked body. The conductive bodies contact the interconnects above the second terrace.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.

Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first insulating region, and a memory portion. The first connector extends in a first direction. The first conductive layer is electrically connected to the first connector, and includes a first planar region, a first overlap region, a first side surface region, and a first crossing side surface region. The second connector extends in the first direction. The second conductive layer is electrically connected to the second connector, and includes a second planar region, a second overlap region, a second side surface region, and a second crossing side surface region. The first insulating region is provided between the first and second conductive layers. The memory portion is connected to the first and second planar regions.

Abstract: A semiconductor device according to an embodiment, includes a stacked body, a plurality of first terraces, a second terrace, a plurality of interconnects, a plurality of conductive bodies. The stacked body includes a plurality of electrode layers. The stacked body includes a stairstep portion at an end portion of the stacked body. The plurality of first terraces are provided in the stairstep portion. The second terrace is provided in the stairstep portion. The plurality of interconnects are provided from the second terrace to the plurality of first terraces. The plurality of interconnects contact one of the plurality of electrode layers at the stairstep portion. The plurality of conductive bodies are provided above the second terrace. The plurality of conductive bodies extend in a stacking direction of the stacked body. The conductive bodies contact the interconnects above the second terrace.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first insulating region, and a memory portion. The first connector extends in a first direction. The first conductive layer is electrically connected to the first connector, and includes a first planar region, a first overlap region, a first side surface region, and a first crossing side surface region. The second connector extends in the first direction. The second conductive layer is electrically connected to the second connector, and includes a second planar region, a second overlap region, a second side surface region, and a second crossing side surface region. The first insulating region is provided between the first and second conductive layers. The memory portion is connected to the first and second planar regions.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.

Abstract: A memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which plural pairs of a first crystal layer made of a first compound and a second crystal layer made of a second compound are alternately stacked. An average composition of the entire resistance change film or an arrangement pitch of the first crystal layers and the second crystal layers are mutually different among the n resistance change films.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes preparing a structure body. In the structure body, a fin extending in a first direction is formed on an upper surface of a semiconductor substrate, a lower-side mask member is provided on the fin, and an upper-side mask member that is wider than the fin and the lower-side mask member is provided on the lower-side mask member. The method includes implanting an impurity into the semiconductor substrate with the upper-side mask member and the lower-side mask member as a mask, removing the upper-side mask member, forming a gate insulator film on a side surface of the fin, forming a conductive film that covers the fin and the lower-side mask member, forming a mask for gate having a pattern extending in a second direction, and removing selectively the conductive film to form a gate electrode.

Abstract: An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.

Abstract: According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A protrusion is formed at a portion of the each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction of the arrangement. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. In the each of the interconnects, the portion having the recess is separated from portions on two sides of the portion having the recess and is separated also from the portion having the protrusion.

Abstract: An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.