Abstract: The present disclosure is directed to searching an image database. A system may include at least one processor comprising circuitry and a memory, wherein the memory includes instructions that, when executed by the circuitry cause the at least one processor to: receive a first user input including one or more scenario descriptors, identify in a database an initial plurality of images based on the first user input and display the initial plurality of images to a user. The processor may be further configured to receive a second user input wherein the second user input identifies at least one of the initial plurality of images. The at least one processor may identify a refined plurality of images in the database based on the one or more scenario descriptors in combination with the second user input and display the refined plurality of images to the user.

Abstract: In an embodiment, a navigation system for a host vehicle may include at least one processor comprising circuitry and a memory. The memory may include instructions that when executed by the circuitry cause the at least one processor to receive at least one image from a camera on a host vehicle, to analyze the at least one image to identify at least one object represented in the image, to generate a feature vector representative of the at least one object, to compare the generated feature vector to a plurality of feature vectors stored in a database and in response to a determination that the generated feature vector does not match an entry in the database, send the generated feature vector to a server, wherein the server is configured to generate an updated feature vector database in response to the generated feature vector sent by the host vehicle navigation system in combination with feature vectors received from a plurality of additional vehicles.

Abstract: Architecture and corresponding methods share resources and synchronize counters in high-speed network integrated circuits. The architecture has at least one counter group comprising several registers, each with two ports. One port receives networking events (e.g., receipt of an-error packet, transmission of a good packet, etc.) via a tri-state bus. The registers in each counter group use a shared hardware memory element, which adds the events for each counter group. The second port is available for asynchronous external read accesses via a second tri-state bus. The architecture synchronizes read requests with events such that read accesses occur during gaps in events. The registers are assigned to several mutually exclusive counter groups such that no two registers in the counter group increment in a basic clock cycle.