Abstract: An image sensor pixel is provided that includes a single-photon avalanche diode (SPAD), an analog counter coupled to a cathode terminal of the SPAD, and a comparator having a first input coupled to a floating diffusion node in the analog counter, a second input configured to receive a reference voltage, and a clock input configured to receive a comparator clock signal from the analog counter. The image sensor pixel can further include an analog memory circuit selectively coupled to an output of the comparator. The analog memory circuit can include a read enable switch coupled between the output of the comparator and a storage node and a plurality of capacitors coupled to the storage node via respective switches.

Abstract: An image sensor may include an array of pixels arranged in rows and columns. Each pixel can include a subpixel circuit and one or more subtraction circuits. Each subpixel circuit can be selectively coupled to neighboring subpixel circuits in the same row via horizontal odd and even switches and can be selectively coupled to neighboring subpixel circuits in the same column via vertical odd and even switches. The horizontal and vertical switches can be turned on in separate phases to store difference values from pairs of neighboring subpixels into the one or more subtraction circuits. The difference values can be read out using comparators and one or more shift registers to output an edge image that includes only edge information.

Abstract: An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

Abstract: An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.