Patents by Inventor Gal Malach
Gal Malach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936570Abstract: A modular switch and a method that includes (a) first tier switching elements that comprise input output (IO) ports; and (b) second tier switching elements that are coupled to the first tier switching elements in a non-blocking manner. The first tier switching elements are configured to perform traffic management of traffic, and perform substantially all egress processing and ingress processing of the traffic; wherein the traffic management comprises load balancing, traffic shaping and flow-based reordering. The second tier switching elements are configured to (a) provide a shared memory space to the first tier switching elements, (b) perform substantially all of the queuing of traffic and (c) send, to the first tier switching elements, status information related to the status of shared memory resources. The first tier switching elements are configured to perform the traffic management based, at least in part, on the status information.Type: GrantFiled: September 22, 2019Date of Patent: March 19, 2024Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 11677673Abstract: A system for managing traffic between servers, the system may include first tier switches that are coupled to the servers; second tier switches that are coupled to the first tier switches and to third tier switches; and controllers. Wherein each first tier switch comprises first queues. Wherein each second tier switch comprises second queues. The controllers are configured to control a traffic between the first tier switches and the second tier switches attributed to the traffic between the servers, (a) on, at least, a queue granularity; (b) while controlling some first queues to provide buffer extension to some second queues, and (c) while controlling some second queues to provide buffer extension to some first queues.Type: GrantFiled: September 6, 2021Date of Patent: June 13, 2023Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 11552884Abstract: A method for managing traffic in a computerized system that may include routers and at least one edge device, the method may include performing traffic management operations for controlling traffic related to the routers while executing a first traffic management operations by the at least one edge device, and executing second traffic management operations by the routers.Type: GrantFiled: September 22, 2020Date of Patent: January 10, 2023Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Publication number: 20220197824Abstract: An elastic memory system that may include memory banks, clients that are configured to obtain access requests associated with input addresses; first address converters that are configured to convert the input addresses to intermediate addresses within a linear address space; address scramblers that are configured to convert the intermediate addresses to physical addresses while balancing a load between the memory banks; atomic operation units; an interconnect that is configured to receive modified access requests that are associated with the physical addresses, and send the modified access requests downstream, wherein atomic modified access requests are sent to the atomic operation units; wherein the atomic operations units are configured to execute the atomic modified access requests; wherein the memory banks are configured to respond to the atomic modified access requests and to non-atomic modified access requests.Type: ApplicationFiled: December 15, 2021Publication date: June 23, 2022Applicant: XSIGHT LABS LTD.Inventors: GUY KOREN, Gal Malach, Carmi Arad
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Patent number: 11251245Abstract: A method for responding to a failure of a main die of a switch data-plane device, the method may include applying a secondary packet forwarding process by multiple chiplets, following the failure of the main die and during at least a part of an execution of a synchronous graceful process that follows the failure of the main die; wherein the multiple chiplets are interconnected to each other by a secondary interconnect; wherein the multiple chiplets and are coupled to the main die by a primary interconnect; wherein the applying of the secondary packet forwarding process is less complex than a primary forwarding process applied by the main die while the main die is functional.Type: GrantFiled: January 21, 2020Date of Patent: February 15, 2022Assignee: XSIGHT LABS LTD.Inventors: Carmi Arad, Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 11115341Abstract: A system for managing traffic between servers, the system may include first tier switches that are coupled to the servers; second tier switches that are coupled to the first tier switches and to third tier switches; and controllers. Wherein each first tier switch comprises first queues. Wherein each second tier switch comprises second queues. The controllers are configured to control a traffic between the first tier switches and the second tier switches attributed to the traffic between the servers, (a) on, at least, a queue granularity; (b) while controlling some first queues to provide buffer extension to some second queues, and (c) while controlling some second queues to provide buffer extension to some first queues.Type: GrantFiled: September 22, 2019Date of Patent: September 7, 2021Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 9171117Abstract: The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.Type: GrantFiled: March 28, 2011Date of Patent: October 27, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Asher Berkovitz, Gal Malach, Eytan Weisberger
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Publication number: 20140013294Abstract: The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.Type: ApplicationFiled: March 28, 2011Publication date: January 9, 2014Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Asher Berkovitz, Gal Malach, Eytan Weisberger
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Patent number: 8286040Abstract: A device having testing capabilities, the device includes: a tested circuit that includes multiple scan chains; a compactor adapted to compress scan chain test responses; a mask unit, connected between the multiple scan chains and the compactor, wherein the mask unit is adapted to mask scan chain test responses outputted by the multiple scan chains during a masking period; and an mask prevention unit, adapted to prevent masking of scan chain test responses during a mask prevention period that at least partially overlaps a mask unit configuration period.Type: GrantFiled: February 9, 2007Date of Patent: October 9, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Gal Malach, Nir Blinky, Lior Moheban
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Publication number: 20100090706Abstract: A device having testing capabilities, the device includes: a tested circuit that includes multiple scan chains; a compactor adapted to compress scan chain test responses; a mask unit, connected between the multiple scan chains and the compactor, wherein the mask unit is adapted to mask scan chain test responses outputted by the multiple scan chains during a masking period; and an mask prevention unit, adapted to prevent masking of scan chain test responses during a mask prevention period that at least partially overlaps a mask unit configuration period.Type: ApplicationFiled: February 9, 2007Publication date: April 15, 2010Applicant: FREESCALE SEMICONDUCTOR ,INC.Inventors: Gal Malach, Nir Blinky, Lior Moheban