Abstract: A method for communication includes mapping transport sequence numbers in headers of data packets received from a network to respective buffers in a memory of a host computer. At least a part of the data from payloads of the received data packets is written directly to the respective buffers.

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.

Abstract: A network device includes a network interface, a host interface, and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host comprising a host processor running a client process. The processing circuitry is configured to receive packets belonging to a message having a message length, the message originating from a peer process, to identify, in at least some of the received packets, application-level information specifying the message length, to determine, based on the identified message length, that the packets of the message already received comprise only a portion of the message, and in response to determining that the client process benefits from receiving less than the entire message, to initiate reporting the packets of the message already received to the client process.

Abstract: An apparatus for cache management includes an interface and a processor. The interface is for communicating with a cache memory configured to store data items. The cache controller is configured to obtain a classification of the data items into a plurality of groups, to obtain respective target capacities for at least some of the groups, each target capacity defining a respective required size of a portion of the cache memory that is permitted to be occupied by the data items belonging to the group, and to cache new data items in the cache memory, or evict cached data items from the cache memory, in accordance with a policy that complies with the target capacities specified for the groups.

Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data communication connections connecting various system components, including the various levels of system memory. Some embodiments may include processing a buffer allotment request and/or a buffer release command in coordination with a system or network operation requiring temporary storage of data in a memory buffer. The buffer allotment request may be capable of indicating the amount of storage space required on the memory buffer to execute the system or network operation. The system may be capable of precluding the system or network operation from executing until there is sufficient space in the memory buffer to complete the operation without evicting operational data from the memory buffer. In some embodiments, the buffer release command may signal completion of the system or network operation and release of the utilized memory buffer space for other operations.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.

Abstract: A network interface device includes a memory to store configuration values associated with a reinforcement learning (RL) routine and a set of RL-related parameters associated with the RL routine, packet processing circuitry to receive network packets, and accelerator circuitry coupled to the memory and the packet processing circuitry. The accelerator circuitry is to: detect a network packet that includes a particular criterion; and execute the RL routine, using the configuration values and in response to detecting the network packet, to employ observation information derived from or associated with the network packet to perform an RL-related action.

Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.

Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

Abstract: A method for approximating a mathematical function defined over a range includes initially dividing at least part of the range into a set of segments. For at least a subset of the segments, the mathematical function is approximated within each segment by a respective approximation polynomial. A series of one or more segment-merging iterations is performed, a given iteration including: selecting adjacent segments as candidates for merging; approximating the mathematical function by a candidate approximation polynomial, over at least a merged segment formed by merging the adjacent segments; and, if approximation of the mathematical function meets a specified condition, updating the set of segments by (i) replacing the adjacent segments with the merged segment and (ii) replacing the approximation polynomials of the adjacent segments with the candidate approximation polynomial.

Abstract: A network device includes a network interface, a host interface, and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host comprising a host processor running a client process. The processing circuitry is configured to receive packets belonging to a message having a message length, the message originating from a peer process, to identify, in at least some of the received packets, application-level information specifying the message length, to determine, based on the identified message length, that the packets of the message already received comprise only a portion of the message, and in response to determining that the client process benefits from receiving less than the entire message, to initiate reporting the packets of the message already received to the client process.

Abstract: Apparatuses, systems, and techniques to improve processing efficiency. In at least one embodiment, a processing unit includes circuitry that reads a vector from memory and multiplies the vector with a scalar value extracted from a scalar field of a vector register. The scalar field may be specified by an immediate field value that is also used to identify an offset used to define a pointer that points to a location in the memory from which to read the vector.

Abstract: Apparatuses, systems, and techniques to improve processing efficiency are provided. In at least one embodiment, a processing unit is described as including circuitry that receives an input vector and applies an activation function to the input vector by performing a hardware approximation of the activation function in a vector manner. The circuitry also generates an output vector based on the activation function.

Abstract: In one embodiment, a processing apparatus includes a processor to train an artificial intelligence model to find a pacing action from which to derive a pacing metric for use in serving content transfer requests.

Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a host processor running a client process. The processing circuitry is configured to receive packets originating from a peer process, to identify, in at least some of the received packets, application level information that is exchanged between the client process and the peer process, and to initiate reporting of one or more of the received packets to the client process, based on the application level information.

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry, and retrieve WRs from the multiple NSQs and execute data transmission operations specified in the WRs retrieved from the multiple NSQs.

Abstract: A method for communication includes mapping transport sequence numbers in headers of data packets received from a network to respective buffers in a memory of a host computer. At least a part of the data from payloads of the received data packets is written directly to the respective buffers.

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.