Patents by Inventor Gamil Cain

Gamil Cain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260170121
    Abstract: An example method of authentication is performed at a memory device that comprises non-volatile memory and control circuitry. The method includes receiving a data request that includes a set of data and a reference digest and generating an authentication digest for the set of data. The method also includes determining whether the reference digest matches the authentication digest. In accordance with a determination that the reference digest matches the authentication digest, performing an operation corresponding to the data request in the non-volatile memory. In accordance with a determination that the reference digest does not match the authentication digest, indicating that the data request is not to be performed.
    Type: Application
    Filed: December 17, 2024
    Publication date: June 18, 2026
    Inventor: Gamil CAIN
  • Publication number: 20260169642
    Abstract: This application is directed to memory methods, systems, and devices for managing secure data and implementing secure operations locally. In one aspect, a memory device includes a non-volatile memory, a memory controller, a secure controller, and an integrated memory enclosure. The non-volatile memory includes a secure memory portion and a data memory portion. The secure memory portion stores secure data, and the data memory portion stores user data. The memory controller is coupled to the data memory portion, and configured to receive a data access request and access the user data in response to the data access request. The secure controller is coupled to the secure memory portion, and configured to access the secure data and implement a secure operation on the secure data. The integrated memory enclosure encloses the secure controller, the memory controller, and the non-volatile memory.
    Type: Application
    Filed: December 16, 2024
    Publication date: June 18, 2026
    Inventors: Wilson YOUNG, Gamil CAIN
  • Publication number: 20240427872
    Abstract: This application is directed to managing custom memory functions in a memory device coupled to a host device in an electronic system. The memory device obtains an information item (e.g., program, data, metadata) used to implement a custom memory function. The memory device receives a host signature and a public key from the host device and authenticates the host signature using the public key. In accordance with an authentication of at least the host signature, the memory device executes the custom memory function based on the information item. In some embodiments, the host device selects a set of memory devices based on a first-come-first-serve order, and the custom memory function is executed at each of the set of memory devices in accordance with an authentication of at least a respective host signature issued by the host device.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 26, 2024
    Inventors: Jordan HOWES, Gamil CAIN
  • Publication number: 20240214200
    Abstract: This application is directed to prime number generation in an electronic device. The electronic device has a first executable and a second executable, and each executable has a unique identifier. The electronic device generates a wrapping key for the first executable and encrypts a prime number with the wrapping key of the first executable to generate an encrypted prime number. The encrypted prime number is stored locally in memory of the electronic device, and is only decryptable by the first executable but not by the second executable. In some embodiments, the first executable extracts the encrypted prime number from the memory of the electronic device, obtains the wrapping key of the first executable, and decrypts the encrypted prime number based on the wrapping key. In an example, the second executable is followed by the first executable, and generates the wrapping key based on a unique identifier of the second executable.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Andre SILVEIRA, Gamil CAIN
  • Patent number: 10929251
    Abstract: A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Peng Li, David J. Pelster, Gamil Cain, Ryan J. Norton
  • Publication number: 20190227884
    Abstract: A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Peng LI, David J. PELSTER, Gamil CAIN, Ryan J. NORTON
  • Publication number: 20190042089
    Abstract: Examples include techniques for determining a storage policy for storing data in a computing system having one or more storage nodes, each storage node including one or more storage devices. One technique includes getting rating information from a storage device of a storage node; assigning the storage device to a storage pool based at least in part on the rating information; and automatically determining a storage policy for the computing system based at least in part on the assigned storage pool and the rating information.
    Type: Application
    Filed: March 2, 2018
    Publication date: February 7, 2019
    Inventors: Anjaneya R. CHAGAM REDDY, Mohan J. KUMAR, Sujoy SEN, Murugasamy K. NACHIMUTHU, Gamil CAIN
  • Publication number: 20190042126
    Abstract: Technologies for storage discovery and reallocation include a compute device. The compute device is to receive, from a data storage sled, storage device data from a storage device located on the data storage sled. The storage device data includes storage device self-test data that defines a result of a self-test performed by the storage device. The compute device is also to determine, in response to the storage device self-test data, whether the storage device fails to satisfy a performance threshold. Further, the compute device is to generate, in response to a determination that the storage device fails to satisfy the performance threshold, an adjustment message for the storage device. The adjustment message instructs the storage device to adjust a performance parameter of the storage device. The compute device is also to send the adjustment message to the storage device.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 7, 2019
    Inventors: Sujoy Sen, Gamil Cain, Teddy Greer, Anjaneya Reddy Chagam Reddy
  • Publication number: 20190036704
    Abstract: A system for verifying the secure erase of a storage device is provided. A storage device controller for the storage device logs the execution of a secure erase command. A storage device controller for the storage device receives an erase verify command from a host. The storage device controller retrieves one or more secure erase log entries from access-limited memory locations in non-volatile memory of the storage device. The storage device controller copies the one or more secure erase log entries to storage device buffer circuitry. The storage device controller secures the one or more secure erase log entries with one or more cryptographic keys to generate an encrypted and/or signed erase verification message. The storage device controller transmits the encrypted and/or signed erase verification message to the host, in response to receipt of the erase verify command.
    Type: Application
    Filed: December 27, 2017
    Publication date: January 31, 2019
    Applicant: Intel Corporation
    Inventors: DOUG DeVETTER, JAMES CHU, ADRIAN PEARSON, GAMIL CAIN, SRIKANTH VARADARAJAN
  • Publication number: 20060221850
    Abstract: An ordered classification procedure includes receiving a packet including a plurality of packet fields having corresponding field values. At least some of the packet fields are parsed to extract at least some of the field values of the packet. The extracted field values are examined using the ordered classification procedure to classify the packet into a flow. An order of the field examinations scheduled within the ordered classification procedure to examine the field values is based at least in part on the field values themselves.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Teresa Buckley, Ellen Deleganes, Shuchi Chawla, Vijay Kesavan, Gamil Cain