Abstract: In a system bus having a master-slave architecture, shared memory controlled by a plurality of registers, master-slave central processing units, and master-slave bus controllers, a process of reading and writing data to the shared memory is disclosed. The process comprises the steps of requesting access to the shared memory by the central processing units by writing a request bit on a first register; reading an access bit on a second register to determine whether the access bit is set and access to shared memory is granted; reading or writing data to the shared memory by the central processing units; and reading the access bit on the second register to determine whether the access bit is cleared and access to the shared memory is complete. The access bit is set by the master-slave bus controller.