Abstract: A method for controlling a stepper motor includes calculating a duty cycle of a current provided to the stepper motor and comparing a difference, between the calculated duty cycle and a base duty cycle of current provided to the stepper motor under a base load condition, to a reference duty cycle value. The method also includes adjusting a peak current level of the current provided to the stepper motor responsive to the comparison.

Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.

Abstract: A driver system operable to supply a drive signal to a motor includes a system input adapted to be coupled to an input voltage and a system output adapted to be coupled to the motor. The driver system includes a high-side transistor which has a first terminal coupled to the system input, a second terminal coupled to the system output, and has a control terminal. The driver system includes a low-side transistor which has a first terminal coupled to the system output, a second terminal coupled to a reference potential terminal, and has a control terminal. The driver system includes a low-side gate control circuit which provides a first level current responsive to a low-side digital control signal transitioning from a low state to a high state and provides a second level current if the output voltage is less than an upper reference voltage.

Abstract: A method for controlling a stepper motor includes calculating a duty cycle of a current provided to the stepper motor and comparing a difference, between the calculated duty cycle and a base duty cycle of current provided to the stepper motor under a base load condition, to a reference duty cycle value. The method also includes adjusting a peak current level of the current provided to the stepper motor responsive to the comparison.

Abstract: A device includes FETs with control terminals. A gate driver circuit causes the FETs to turn on and to enter a high-impedance state in response to an OCP signal. A current sense circuit senses an FET current through the FETs and sends the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for longer than an OCP deglitch period. A test sequencer, in response to receiving an external test mode signal, sets the OCP current to a preset OCP test current, sets the OCP deglitch period to a preset OCP deglitch test period, and causes the gate driver circuit to turn on the plurality of FETs.

Abstract: A stepper motor controller includes a first error amplifier, a second error amplifier, and a comparator. The first error amplifier has a first input adapted to be coupled to a current sensor to receive a sensed drive current, a second input adapted to receive an expected drive current and an output to provide a first error signal based on a comparison of the sensed drive current and the expected drive current. The second error amplifier has a first input adapted to be coupled to a voltage sensor to receive a sensed drive voltage, a second input coupled to the output of the first error amplifier and an output to provide a second error signal based on a comparison of the sensed drive voltage and the first error signal. The comparator has a first input adapted to receive a reference signal, a second input coupled to the output of the second error amplifier and an output to provide a stepper motor control signal based on a comparison of the reference signal and the error signal.

Abstract: A device includes FETs with control terminals. A gate driver circuit causes the FETs to turn on and to enter a high-impedance state in response to an OCP signal. A current sense circuit senses an FET current through the FETs and sends the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for longer than an OCP deglitch period. A test sequencer, in response to receiving an external test mode signal, sets the OCP current to a preset OCP test current, sets the OCP deglitch period to a preset OCP deglitch test period, and causes the gate driver circuit to turn on the plurality of FETs.

Abstract: A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

Abstract: A driver circuit includes a first switch which has a first terminal coupled to a voltage supply terminal, a second terminal coupled to a high-side gate, and a third terminal coupled to receive a voltage supply enable signal. The first switch is operable to connect the voltage supply terminal to the high-side gate responsive to the voltage supply enable signal. The driver circuit includes a second switch which has a first terminal coupled to a charge pump terminal, a second terminal coupled to the high side gate, and a third terminal coupled to receive a charge pump enable signal. The second switch is operable to connect the charge pump terminal to the high-side gate responsive to the charge pump enable signal.

Abstract: A driver circuit includes a first switch which has a first terminal coupled to a voltage supply terminal, a second terminal coupled to a high-side gate, and a third terminal coupled to receive a voltage supply enable signal. The first switch is operable to connect the voltage supply terminal to the high-side gate responsive to the voltage supply enable signal. The driver circuit includes a second switch which has a first terminal coupled to a charge pump terminal, a second terminal coupled to the high side gate, and a third terminal coupled to receive a charge pump enable signal. The second switch is operable to connect the charge pump terminal to the high-side gate responsive to the charge pump enable signal.

Abstract: A driver circuit includes a high side transistor, a low side transistor, a first trigger circuit, and a second trigger circuit. The high side transistor has a first control terminal and a first current path coupled between a first voltage terminal and an output voltage terminal. The low side transistor has a second control terminal and a second current path coupled between the output voltage terminal and ground. The first trigger circuit is coupled to the first control terminal, the first voltage terminal, and the output voltage terminal. The first trigger circuit is operable to protect the high side transistor. The second trigger circuit is coupled to the second control terminal, the first trigger circuit, and ground. The second trigger circuit is operable to protect the low side transistor.

Abstract: An integrated circuit including an autosleep circuit and a voltage regulator. The autosleep circuit includes a latch, a voltage detection circuit outputting a signal to a set input of the latch responsive to a voltage at its input exceeding a threshold voltage, and a delay timer outputting a signal to a reset input of the latch responsive to inactivity at one or more input terminals. A voltage regulator is configured to generate a voltage for biasing a subsystem such as digital logic, and is also the input voltage to the voltage detection circuit. The voltage regulator includes a plurality of transistors in parallel, one gated by the output of the latch and each of the others gated by one of the one or more input terminals. The voltage regulator includes an output leg that generates the output voltage responsive to one of the parallel transistors being turned on.

Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.

Abstract: A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current sense FET is coupled between a current source and the lower supply voltage to provide a reference current that includes a peak current limit at a sensing node. A current-sense comparator has a first input coupled to the sensing node, a second input coupled to the second output node and an output coupled to send an output signal towards a driver control circuit. A FET linear detection circuit is coupled to receive a gate voltage of an active low-side power FET and has an output coupled to enable the current-sense comparator when the active low-side power FET is operating in a linear region.

Abstract: A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current sense FET is coupled between a current source and the lower supply voltage to provide a reference current that includes a peak current limit at a sensing node. A current-sense comparator has a first input coupled to the sensing node, a second input coupled to the second output node and an output coupled to send an output signal towards a driver control circuit. A FET linear detection circuit is coupled to receive a gate voltage of an active low-side power FET and has an output coupled to enable the current-sense comparator when the active low-side power FET is operating in a linear region.

Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.

Abstract: A driver circuit comprises a first buffer receiving a control signal, and a first transistor coupled to first buffer and an output. A second transistor is coupled to a first current mirror and the output. A third transistor is coupled to the output and an inverter. A fourth transistor receives the inverter's output at its control input and is coupled to the output. A fifth transistor is coupled to third transistor. The second, third, and fifth transistors receive supply voltage at their respective control inputs. A sixth transistor receives the control signal's inverse at its control input and is coupled to fifth transistor and a second current mirror. A current source is coupled to second current mirror and a second buffer. A seventh transistor receives the second buffer's output at its control input and is coupled to first buffer. An eighth transistor is coupled to first buffer and seventh transistor.

Abstract: A driver circuit comprises a first transistor coupled to a second transistor, and a third transistor coupled to the first and second transistor and to a first current mirror. An output of the first current mirror is provided to a control input of the second transistor. A second current mirror is coupled to the output of the first current mirror. A first current source, a second current source, and a fourth transistor are coupled to the second current mirror. The second current source is further coupled to a fifth transistor. A sixth transistor is coupled to the fifth transistor and to a third current mirror. In some implementations, the driver circuit is coupled to a low side transistor in an H bridge driver and the second transistor is matched to the low side transistor.