Patents by Inventor Ganapati N. Srinivasa
Ganapati N. Srinivasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8984228Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.Type: GrantFiled: December 13, 2011Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Yen-Cheng Liu, Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur, Bahaa Fahim
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Publication number: 20150006776Abstract: A particular message is received at a first ring stop connected to a first ring of a mesh interconnect including a plurality of rings oriented in a first direction and a plurality of rings oriented in a second direction substantially orthogonal to the first direction. The particular message is injected on a second ring of the mesh interconnect. The first ring is oriented in the first direction, the second ring is oriented in the second direction, and the particular message is to be forwarded on the second ring to another ring stop of a destination component connected to the second ring.Type: ApplicationFiled: June 29, 2013Publication date: January 1, 2015Inventors: Yen-Cheng Liu, Jason W. Horihan, Krishnakumar Ganapathy, Umit Y. Ogras, Allen W. Chu, Ganapati N. Srinivasa
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Publication number: 20140298140Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.Type: ApplicationFiled: December 22, 2011Publication date: October 2, 2014Inventors: Theodros Yigzaw, Oded Lempel, Hisham Hafi, Geeyarpuram N Santhanakrisnan, Jose A Vargas, Ganapati N Srinivasa, Mohan J Kumar, Larisa Novakovsky, Lihu Rappoport, Chen Koren, Julius Yuli Mandelblat
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Publication number: 20140281457Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.Type: ApplicationFiled: March 29, 2013Publication date: September 18, 2014Inventors: Elierzer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
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Publication number: 20140223226Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: December 22, 2011Publication date: August 7, 2014Inventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrushnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Publication number: 20140189299Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
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Publication number: 20140189704Abstract: A heterogeneous processor architecture is described.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
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Publication number: 20140189301Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Ganapati N. Srinivasa, Eliezer Weissmann, Guarav Khanna, Mishali Naik, Russell J. Fenger, Andrew D. Henroid, Dheeraj R. Subbareddy, David A. Koufaty, Paolo Narvaez
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Publication number: 20140189302Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Dheeraj R. Subbareddy, Ganapati N. Srinivasa, David A. Koufaty, Scott D. Hahn, Mishali Naik, Paolo Narvaez, Abirami Prabhakaran, Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Eliezer Weissmann, Paul Brett, Gaurav Khanna, Russell J. Fenger
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Publication number: 20140189377Abstract: An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Dheeraj R. Subbareddy, Ganapati N. Srinivasa, Eugene Gorbatov, Scott D. Hahn, David A. Koufaty, Paul Brett, Abirami Prabhakaran
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Publication number: 20140189297Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Gaurav Khanna, Russell J. Fenger, Bryant E. Bigbee, Andrew D. Henroid
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Publication number: 20140181830Abstract: According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Inventors: Mishali Naik, Ganapati N. Srinivasa, Alon Naveh, Inder M. Sodhi, Paolo Narvaez, Eugene Gorbatov, Eliezer Weissmann, Andrew D. Henroid, Andrew J. Herdrich, Guarav Khanna, Scott D. Hahn, Paul Brett, David A. Koufaty, Dheeraj R. Subbareddy, Abirami Prabhakaran
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Patent number: 8751714Abstract: Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry.Type: GrantFiled: September 24, 2010Date of Patent: June 10, 2014Assignee: Intel CorporationInventors: Robert J. Safranek, Debendra Das Sharma, Ganapati N. Srinivasa
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Publication number: 20130151782Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Inventors: Yen-Cheng Liu, Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur, Bahaa Fahim
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Publication number: 20120079156Abstract: Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Robert J. Safranek, Debendra Das Sharma, Ganapati N. Srinivasa
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Patent number: 6897857Abstract: A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.Type: GrantFiled: May 22, 2003Date of Patent: May 24, 2005Assignee: Intel CorporationInventors: Ganapati N. Srinivasa, Gopalan Ramanujam, Glenn M. Lewis, Calvin J. Lin, Jeffrey A. Larson, Arunachalam S. Prakash
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Publication number: 20030193498Abstract: A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.Type: ApplicationFiled: May 22, 2003Publication date: October 16, 2003Inventors: Ganapati N. Srinivasa, Gopalan Ramanujam, Glenn M. Lewis, Calvin J. Lin, Jeffrey A. Larson, Arunachalam S. Prakash
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Patent number: 6618046Abstract: A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.Type: GrantFiled: September 29, 2000Date of Patent: September 9, 2003Assignee: Intel CorporationInventors: Ganapati N. Srinivasa, Gopalan Ramanujam, Glenn M. Lewis, Calvin J. Lin, Jeffrey A. Larson, Arunachalam S. Prakash