Patents by Inventor Ganapati Srinivasa

Ganapati Srinivasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230315738
    Abstract: Methods and systems are provided for a platform and language agnostic method for generating inter-and intra-data type aggregations of heterogeneous disparate data upon which various operations can be performed without altering the structure of the query or resulting distributed data set representation to account for which specific data sources are included in the query.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventors: Ganapati Srinivasa, Melvin Lathara, Jaclyn Smith, Nalini Ganapati, Hollis Wright, Kavya Kannan
  • Patent number: 11727010
    Abstract: Methods and systems are provided for a platform and language agnostic method for generating inter-and intra-data type aggregations of heterogeneous disparate data upon which various operations can be performed without altering the structure of the query or resulting distributed data set representation to account for which specific data sources are included in the query.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 15, 2023
    Assignee: Omics Data Automation, Inc.
    Inventors: Ganapati Srinivasa, Melvin Lathara, Brian Hill, Jaclyn Smith, Nalini Ganapati, Hollis Wright
  • Publication number: 20230251702
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 10, 2023
    Applicant: Tahoe Research, Ltd.
    Inventors: Yen-Cheng LIU, P. Keong OR, Krishnakanth V. SISTLA, Ganapati SRINIVASA
  • Publication number: 20220108786
    Abstract: Methods and systems are provided for viewing multi-modal data in three dimensions. In one example, a method for visualizing and manipulating multi-modal features of a plurality of data objects includes accessing a plurality of datasets associated with a subject of interest, where data in the plurality of datasets changes in real-time; displaying a hub object representing the subject of interest; dynamically displaying a plurality of axis objects associated with the subject of interest, each comprising a representation of a summary metric of a respective dataset of the plurality of datasets and each displayed proximate the hub object, including adjusting a length and/or intensity of one or more of the plurality of axis objects as the data change; and in response to selection of a first axis object, displaying a first track object including a plurality of representations of data points within a first dataset of the plurality of datasets.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 7, 2022
    Inventors: Hollis Wright, Ganapati Srinivasa
  • Publication number: 20210397612
    Abstract: Methods and systems are provided for a platform and language agnostic method for generating inter-and intra-data type aggregations of heterogeneous disparate data upon which various operations can be performed without altering the structure of the query or resulting distributed data set representation to account for which specific data sources are included in the query.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 23, 2021
    Inventors: Ganapati Srinivasa, Melvin Lathara, Brian Hill, Jaclyn Smith, Nalini Ganapati, Hollis Wright
  • Patent number: 11144108
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 12, 2021
    Assignee: INTEL CORPORATION
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa
  • Patent number: 11138201
    Abstract: Methods and systems are provided for a platform and language agnostic method for generating inter- and intra-data type aggregations of heterogenous disparate data upon which various operations can be performed without altering the structure of the query or resulting distributed data set representation to account for which specific data sources are included in the query.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 5, 2021
    Assignee: OMICS DATA AUTOMATION, INC.
    Inventors: Ganapati Srinivasa, Melvin Lathara, Brian Hill, Jaclyn Smith, Nalini Ganapati, Hollis Wright
  • Publication number: 20210064117
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: Yen-Cheng LIU, P. Keong OR, Krishnakanth V. SISTLA, Ganapati SRINIVASA
  • Publication number: 20200388033
    Abstract: Methods and systems are provided for automatically classifying cells in a histological stained image. In an example, a method includes automatically classifying a plurality of cells in an image of a biological sample stained with a histological stain using a classification model, the classification model trained with a plurality of automatically-classified pseudo-stained images each generated from a respective immunofluorescent image.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 10, 2020
    Inventors: Kevin Lee Matlock, Ganapati Srinivasa, Carlo B. Bifulco, Brian Donald Piening
  • Publication number: 20190163679
    Abstract: Methods and systems are provided for a platform and language agnostic method for generating inter-and intra-data type aggregations of heterogenous disparate data upon which various operations can be performed without altering the structure of the query or resulting distributed data set representation to account for which specific data sources are included in the query.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 30, 2019
    Inventors: Ganapati Srinivasa, Melvin Lathara, Brian Hill, Jaclyn Smith, Nalini Ganapati, Hollis Wright
  • Patent number: 10185566
    Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Alon Naveh, Yuval Yosef, Eliezer Weissmann, Anil Aggarwal, Efraim Rotem, Avi Mendelson, Ronny Ronen, Boris Ginzburg, Michael Mishaeli, Scott D. Hahn, David A. Koufaty, Ganapati Srinivasa, Guy Therien
  • Publication number: 20170160171
    Abstract: Immunohistochemical (IHC) techniques that enable the sequential evaluation of at least seven biomarkers in one formalin-fixed paraffin-embedded (FFPE) tissue section are disclosed. The methods involve high-throughput multiplexed, quantitative IHC imaging, sequential IHC with iterative labeling, digital scanning, image coregistration and merging, and subsequent stripping of sections.
    Type: Application
    Filed: November 18, 2016
    Publication date: June 8, 2017
    Inventors: Takahiro Tsujikawa, Lisa M. Coussens, Rohan Borkar, Vahid Azimi, Sushil Kumar, Ganapati Srinivasa
  • Publication number: 20170017292
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • Publication number: 20170017286
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • Patent number: 9501129
    Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D. Gilbert
  • Publication number: 20160195913
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: December 17, 2015
    Publication date: July 7, 2016
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • Patent number: 9367112
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: June 14, 2016
    Assignee: INTEL CORPORATION
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa
  • Publication number: 20150127962
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 7, 2015
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • Patent number: 8966299
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P Keong Or, Krishnakanth Sistla, Ganapati Srinivasa
  • Patent number: 8914650
    Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D. Gilbert