Patents by Inventor Ganesh Ananthaswamy
Ganesh Ananthaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8891715Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.Type: GrantFiled: June 27, 2012Date of Patent: November 18, 2014Assignee: Analog Devices, Inc.Inventors: Ganesh Ananthaswamy, Sudheesh A. Somanathan
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Patent number: 8885763Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.Type: GrantFiled: August 22, 2011Date of Patent: November 11, 2014Assignee: Analog Devices, Inc.Inventor: Ganesh Ananthaswamy
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Publication number: 20120268191Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: ANALOG DEVICES, INC.Inventors: Ganesh Ananthaswamy, Sudheesh A. Somanathan
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Publication number: 20120207229Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.Type: ApplicationFiled: August 22, 2011Publication date: August 16, 2012Applicant: ANALOG DEVICES, INC.Inventor: Ganesh ANANTHASWAMY
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Patent number: 7746186Abstract: Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error.Type: GrantFiled: January 29, 2008Date of Patent: June 29, 2010Assignee: Analog Devices, Inc.Inventor: Ganesh Ananthaswamy
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Publication number: 20090189707Abstract: Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error.Type: ApplicationFiled: January 29, 2008Publication date: July 30, 2009Inventor: Ganesh Ananthaswamy
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Patent number: 7477170Abstract: A sample rate conversion is accomplished by presenting to a numerically controlled oscillator (NCO) register a clock input at the desired output rate; first-modifying the NCO register contents responsive to a first factor; determining when the first modified NCO register contents are in a predetermined range and in response to the first modified NCO register contents not being in the predetermined range, presenting the first modified NCO register contents to the input of the NCO register; second-modifying, responsive to a second factor, the first modified NCO register contents when the first modified NCO register contents are within the predetermined range and presenting it to the input of the NCO register; and fetching samples, in response to the first-modified NCO register contents being in the predetermined range and interpolating them to produce a resultant sample value at the output rate, and in response to the contents not being in the predetermined range to interpolate the previous sample to produce aType: GrantFiled: May 9, 2007Date of Patent: January 13, 2009Assignee: Analaog Devices, Inc.Inventor: Ganesh Ananthaswamy
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Publication number: 20080279319Abstract: A sample rate conversion is accomplished by presenting to a numerically controlled oscillator (NCO) register a clock input at the desired output rate; first-modifying the NCO register contents responsive to a first factor; determining when the first modified NCO register contents are in a predetermined range and in response to the first modified NCO register contents not being in the predetermined range, presenting the first modified NCO register contents to the input of the NCO register; second-modifying, responsive to a second factor, the first modified NCO register contents when the first modified NCO register contents are within the predetermined range and presenting it to the input of the NCO register; and fetching samples, in response to the first-modified NCO register contents being in the predetermined range and interpolating them to produce a resultant sample value at the output rate, and in response to the contents not being in the predetermined range to interpolate the previous sample to produce aType: ApplicationFiled: May 9, 2007Publication date: November 13, 2008Inventor: Ganesh Ananthaswamy
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Patent number: 7302025Abstract: An efficient approach to generating the bias resulting during the joint equalization/decoding of a Complementary-Code-Keying (CCK) based system is provided that includes a bias generator system having a plurality of inputs responsive only to feedback filter coefficients, the bias generator generating, based upon said feedback filter coefficients, a plurality of output signals corresponding to the bias of a Fast Walsh Transform system for cancelling the bias.Type: GrantFiled: April 3, 2004Date of Patent: November 27, 2007Assignee: Analog Devices, Inc.Inventor: Ganesh Ananthaswamy
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Publication number: 20050069033Abstract: An efficient approach to generating the bias resulting during the joint equalization/decoding of a Complementary-Code-Keying (CCK) based system is provided that includes a bias generator system having a plurality of inputs responsive only to feedback filter coefficients, the bias generator generating, based upon said feedback filter coefficients, a plurality of output signals corresponding to the bias of a Fast Walsh Transform system for cancelling the bias.Type: ApplicationFiled: April 3, 2004Publication date: March 31, 2005Inventor: Ganesh Ananthaswamy