Abstract: A physical system is simulated using a model including a plurality of elements in a mesh or grid. The elements are divided into partitions processed by different processing units. For some time steps, state data is transmitted between partitions and used to calculate flux data for updating the state of edge elements of the partitions. Periodically, transmission of state data is suppressed, and flux data is obtained by linear interpolation based on past flux data. Alternatively, flux data is obtained by processing state variables of an edge element and past flux data using a machine learning model, such as a DNN. Whether to suppress transmission of state data may be determined based on one or both of (a) uncertainty in an output of the machine learning model (e.g., Bayesian neural network) and (b) complexity of model of the physical system (e.g., spatial or temporal gradients).

Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.

Abstract: Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

Abstract: A processing device includes a zero detection circuit to determine that an operand of a first instruction is zero and instruction conversion logic coupled with the zero detection circuit to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.

Abstract: A physical system is simulated using a model including a plurality of elements in a mesh or grid. The elements are divided into partitions processed by different processing units. For some time steps, flux data is transmitted between partitions for updating the state of edge elements of the partitions. Periodically, transmission of flux data is suppressed and flux data is obtained by linear interpolation based on past flux data. Alternatively, flux data is obtained by processing state variables of an edge element and past flux data using a machine learning model, such as a DNN.

Abstract: An approach is provided for using machine learning to provide compensation for roundoff error in algorithmic computations. The approach includes training a machine learning model based low precision data and corresponding high precision data. The low precision data includes pairs of low precision values of a specific datatype that correspond to pairs of high precision values from the high precision data. The high precision data includes pairs of high precision values of a specific datatype that correspond to the pairs of low precision values from the low precision data. When the machine learning model has been trained, the machine learning model is used as a basis for determining a compensation value is used to compensate for roundoff error in a particular algorithmic computation. Techniques discussed herein provide compensation for roundoff error during otherwise unstable computations, enabling high-performance computing and other scientific applications to use lower precision data types more readily.

Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.

Abstract: A processing device includes a zero detection circuit to determine that an operand of a first instruction is zero and instruction conversion logic coupled with the zero detection circuit to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.

Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

Abstract: A method includes receiving from a compute element a command for performing a requested operation on data stored in a memory device, and in response to receiving the command, performing the requested operation by generating a plurality of memory access requests based on the command and issuing the plurality of memory access requests to the memory device.

Abstract: Subject matter disclosed herein may relate to storage and/or processing of signals and/or states representative of neural network parameters in a computing device, and may relate more particularly to compressing signals and/or states representative of neural network nodes in a computing device.

Abstract: Subject matter disclosed herein may relate to storage of signals and/or states representative of parameters in a computing device, and may relate more particularly to storage of signals and/or states representative of neural network parameters in a computing device.

Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.

Abstract: Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

Abstract: Subject matter disclosed herein may relate to storage of signals and/or states representative of parameters in a computing device, and may relate more particularly to storage of signals and/or states representative of neural network parameters in a computing device.

Abstract: Subject matter disclosed herein may relate to storage and/or processing of signals and/or states representative of neural network parameters in a computing device, and may relate more particularly to compressing signals and/or states representative of neural network nodes in a computing device.

Abstract: There is disclosed data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks, each of said data blocks comprising a plurality of bits, said data store comprising at least one faulty bit within at least some of said data blocks.