Abstract: In order to provide an export of trace data related to a block repeat instruction, a trace unit, upon identification of a group of packets applied thereto which are an instruction block that is to be repeated, forwards all the packets comprising the instruction block to a trace export unit. The trace unit saves a portion of the block instruction that permits the identification of the block instruction. When a next of the block instructions being repeated is identified, the trace unit compares the stored portion of the block instruction with the equivalent portion in the newly received block instruction. When the portions are the same, only the header packet of the block instruction is forwarded to the host processing unit. According to another embodiment of the present invention, a preselected number of complete instruction blocks are forwarded to the host processing unit before the trace unit forwards only the header packet.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO (800) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M+K, P+Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC13LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P+Q).