Patents by Inventor Ganesh Rao
Ganesh Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962614Abstract: Systems and methods for cloud security monitoring and threat intelligence in accordance with embodiments of the invention are disclosed. In one embodiment, a process for monitoring and remediation of security threats includes generating a threat model using a first portion of activity data, identifying, based upon the threat model, a threat using a second portion of activity data, selecting a security policy to implement in response to the identified threat, identifying cloud security controls in a remotely hosted cloud application server system to modify in accordance with the selected security policy, establishing a secure connection to the remotely hosted cloud application server system using login credentials associated with a tenant account with the cloud application, and sending instructions to the remotely hosted cloud application server system to set the identified cloud security controls with respect to the tenant account in accordance with the selected security policy.Type: GrantFiled: February 12, 2021Date of Patent: April 16, 2024Assignee: Oracle International CorporationInventors: Ganesh Kirti, Rohit Gupta, Kamalendu Biswas, Ramana Rao Satyasai Turlapati
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Patent number: 11947831Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.Type: GrantFiled: June 2, 2022Date of Patent: April 2, 2024Assignee: Micron Technology, Inc.Inventors: Zhenming Zhou, Murong Lang, Ching-Huang Lu, Nagendra Prasad Ganesh Rao
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Patent number: 11936731Abstract: An illustrative method includes receiving a request to create a storage volume; identifying, based on the request and on a configuration file propagated among a plurality of storage nodes in a cluster, status indicators of the storage nodes; identifying, based on the request, a size of the storage volume; identifying, based on the request, a replication factor representing a number of storage nodes that are to be replicated within a cluster for the storage volume; identifying, based on one or more characteristics associated with the storage volume, a traffic priority for the storage volume, the traffic priority representing a hierarchy that determines and prioritizes which traffic is allocated to available hardware and network resources in a particular order; creating, based on the status indicators, the size, the replication factor, and the traffic priority, the storage volume on one or more of the plurality of storage nodes.Type: GrantFiled: May 8, 2023Date of Patent: March 19, 2024Assignee: Pure Storage, Inc.Inventors: Goutham Rao, Vinod Jayaraman, Ganesh Sangle
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Patent number: 11935023Abstract: A payment-enabled mobile device is placed in communication with a POS (point of sale) terminal to facilitate a purchase transaction. A user selects a payment account in the payment-enabled mobile device. Payment credentials are transmitted from the payment-enabled mobile device to the POS terminal. The payment credentials include a PAN-length identifier that identifies an issuer of the selected payment account.Type: GrantFiled: April 19, 2021Date of Patent: March 19, 2024Assignee: MASTERCARD INTERNATIONAL INCORPORATEDInventors: Jason J. Lacoss-Arnold, Chandrasekhar Rao Nadella, Jeffrey L. Altemueller, Ganesh L. Iyer
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Publication number: 20240087655Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Nagendra Prasad Ganesh Rao, Paing Z. Htet, Sead Zildzic, JR., Thomas Fiala, Jian Huang, Zhenming Zhou
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Patent number: 11928143Abstract: Systems of the present disclosure may ingest content from a plurality of data sources with the content including ingested documents referencing entities and events relevant to the ESG signals. The content may be stored in a content database. The System may also identify metadata and a body of text associated with each document to produce a set of preprocessed documents. An entity may be tagged to a first preprocessed document from the set of preprocessed documents, and the document may include a first document identifier. The System may generate an event score related to a first ESG signal including a direction and a magnitude associated with an event identified in the body of text. The event score may be tagged to the document. The system may write to an unstructured data set the document identifier in association with the tagged entity and the tagged event score for delivery.Type: GrantFiled: July 27, 2020Date of Patent: March 12, 2024Inventors: Philip Kim, Stephen Matthew Malinak, Ganesh Rao, Eli Reisman, Yang Ruan, Faithlyn Tulloch, Eugene Wong
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Patent number: 11923001Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.Type: GrantFiled: January 20, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Tingjun Xie, Jiangli Zhu, Nagendra Prasad Ganesh Rao, Sead Zildzic
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Publication number: 20240071534Abstract: Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, initiates a failed byte count read operation on the segment of the memory array to determine a failed byte count, and reads metadata stored in a flag byte corresponding to the segment of the memory array concurrently with the failed byte count read operation. The control logic further configures one or more parameters associated with the read operation based on the failed byte count and at least a portion of the metadata read from the flag byte.Type: ApplicationFiled: August 23, 2023Publication date: February 29, 2024Inventor: Nagendra Prasad Ganesh Rao
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Publication number: 20230393752Abstract: An example system can include a memory component and a processing device. The memory component can include a group of memory cells. The processing device can be coupled to the memory component. The processing device can be configured to use a first voltage window for a set of memory cells of the group of memory cells during a first time period. The processing device can be configured to determine that an error rate of a sub-set of the set of memory cells is above a threshold error rate. The processing device can be configured to, in response to the determination that the error rate of the sub-set of memory cells is above the threshold error rate, use a second voltage window for the set of memory cells of the group of memory cells during a second time period.Type: ApplicationFiled: August 12, 2022Publication date: December 7, 2023Inventors: Zhenming Zhou, Nagendra Prasad Ganesh Rao, Joshua C. Garrison, Jian Huang
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Publication number: 20230393776Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Inventors: Zhenming Zhou, Murong Lang, Ching-Huang Lu, Nagendra Prasad Ganesh Rao
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Publication number: 20230368845Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.Type: ApplicationFiled: April 24, 2023Publication date: November 16, 2023Inventors: Nagendra Prasad Ganesh Rao, Paing Z. Htet, Sead Zildzic, JR., Thomas Fiala
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Publication number: 20230352098Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.Type: ApplicationFiled: April 10, 2023Publication date: November 2, 2023Inventors: Nagendra Prasad Ganesh Rao, Dheeraj Srinivasan, Paing Z. Htet, Sead Zildzic, JR., Violante Moschiano
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Publication number: 20230307058Abstract: A first program pass of a multi-pass program operation is caused to be performed at a memory array. A first program voltage is applied to a wordline of a block of the memory array to program one or more memory cells during the first program pass. Subsequent to the first program pass of the multi-pass program operation, a pre-read operation is caused to be performed to read data corresponding to the first program pass and from the one or more memory cells. Whether a shift of a threshold voltage corresponding to the one or more memory cells satisfies a condition related to a threshold voltage change is determined based on the pre-read operation. Responsive to determining that the shift of the threshold voltage satisfies the condition, an updated second program voltage of a second program pass of the multi-pass program operation is determined.Type: ApplicationFiled: February 15, 2023Publication date: September 28, 2023Inventors: Nagendra Prasad Ganesh Rao, Sead Zildzic, JR.
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Publication number: 20230206997Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.Type: ApplicationFiled: January 20, 2022Publication date: June 29, 2023Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Tingjun Xie, Jiangli Zhu, Nagendra Prasad Ganesh Rao, Sead Zildzic
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Publication number: 20230115298Abstract: Described herein is a method of controlling the growth of undesirable vegetation weedy Glycine max, the method including treating the locus at which control is desired with a synergistic composition including glufosinate, and at least one herbicide selected from the group consisting of nitrophenyl ether class herbicides; imidazolinone class herbicides; organophosphorous class herbicides; dicarboximide class herbicides; phenoxyacetic class herbicides; pyridine class herbicides; cyclohexene oxime class herbicides; aryloxyphenoxypropionic class herbicides; triazolone class herbicides; and uracil class herbicides.Type: ApplicationFiled: March 10, 2022Publication date: April 13, 2023Inventors: Giuvan Lenz, Ganesh Rao
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Publication number: 20230116683Abstract: Described herein is a method of controlling the growth of undesirable vegetation weedy Brachiaria decumbens, the method including treating the locus at which control is desired with a synergistic composition including glufosinate.Type: ApplicationFiled: March 10, 2022Publication date: April 13, 2023Inventors: Giuvan Lenz, Ganesh Rao
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Publication number: 20230116080Abstract: Described herein is a method of controlling the growth of undesirable vegetation weedy Eleusine indica, the method including treating the locus at which control is desired with a synergistic composition including glufosinate combinations.Type: ApplicationFiled: March 10, 2022Publication date: April 13, 2023Inventors: Giuvan Lenz, Ganesh Rao
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Publication number: 20230116377Abstract: Described herein is a method of controlling the growth of undesirable vegetation weedy Spermacoce latifolia, the method including treating the locus at which control is desired with a synergistic composition including glufosinate combinations.Type: ApplicationFiled: March 10, 2022Publication date: April 13, 2023Inventors: Giuvan Lenz, Ganesh Rao
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Publication number: 20230044424Abstract: The present invention relates to a continuous process for preparation of a stable agrochemical composition in microreactor processing system. The present invention also provides a stable agrochemical composition having mean particle size distribution and method of controlling undesired vegetation with said composition.Type: ApplicationFiled: January 6, 2021Publication date: February 9, 2023Inventors: Ferdinando Marcos Lima Silva, Giuvan Lenz, Ganesh Rao, Achintya Mondal, Milind Jagannath Pimpale
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Publication number: 20220277044Abstract: Systems of the present disclosure may ingest content from a plurality of data sources with the content including ingested documents referencing entities and events relevant to the ESG signals. The content may be stored in a content database. The System may also identify metadata and a body of text associated with each document to produce a set of preprocessed documents. An entity may be tagged to a first preprocessed document from the set of preprocessed documents, and the document may include a first document identifier. The System may generate an event score related to a first ESG signal including a direction and a magnitude associated with an event identified in the body of text. The event score may be tagged to the document. The system may write to an unstructured data set the document identifier in association with the tagged entity and the tagged event score for delivery.Type: ApplicationFiled: July 27, 2020Publication date: September 1, 2022Inventors: PHILIP KIM, STEPHEN MATTHEW MALINAK, GANESH RAO, ELI RISMAN, YANG RUAN, FAITHLYN TULLOCH, EUGENE WONG