Abstract: Techniques for automatically providing per tenant weighted DCMP over shared transport interfaces and automated flow has load balancing are described. The techniques may include onboarding, by an SD-WAN controller, the tenant with a resource profile to a first multi-tenant edge device, where the resource profile defines a traffic allowance per transport interface for the tenant on the first multi-tenant edge device. The SD-WAN controller receives, from the first multi-tenant edge device, information including a first weight per transport interface of the first multi-tenant edge device for the tenant. The SD-WAN controller transmits the information to a second multi-tenant device. The SD-WAN controller receives, from the second multi-tenant edge device, information including a second weight per transport interface of the second multi-tenant edge device, and transmits the information to the first multi-tenant edge device.

Abstract: Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.

Abstract: An access probe existing and generated within a base station to simulate a mobile terminal for the purpose of testing base station receive functionality within a communications system. The access probe data is injected at baseband rather than at RF to eliminate the need for analog/RF circuitry. The access probe performs injection at the front end of the base station receiver to exercise as much receive data path as possible. A unique ID is embedded in the access probes so that the communications system is aware which probes within a sequence were received successfully and at what power level. Within in-field applications, the unique ID allows the communications system to distinguish simulated access probes from those corresponding to real mobiles.

Abstract: Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system in provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user.

Abstract: Methods and apparatus for performing finger de-spreading and MRC combining are provided. A large antenna buffer is used to buffer all the finger signals of the same user so that the receiver can do both de-spreading and MRC at the same time without buffering the de-spreading finger symbols. For each user, a reference time is introduced to align all the finger signals of the same user in the Antenna Buffer. The reference time delay is used to generate the PN codes for de-spreading, as well as to count the number of symbols in a PCG or a frame. Methods for antenna buffer arrangement, interpolating filter implementation, channel estimation and MRC for traffic data channels, timing for the user's finger signal de-spreading and MRC, long code and short code generation for de-spreading, new finger allocation and finger timing adjustment.

Abstract: Methods and apparatus for performing finger de-spreading and MRC combining are provided. A large antenna buffer is used to buffer all the finger signals of the same user so that the receiver can do both de-spreading and MRC at the same time without buffering the de-spreading finger symbols. For each user, a reference time is introduced to align all the finger signals of the same user in the Antenna Buffer. The reference time delay is used to generate the PN codes for de-spreading, as well as to count the number of symbols in a PCG or a frame. Methods for antenna buffer arrangement, interpolating filter implementation, channel estimation and MRC for traffic data channels, timing for the user's finger signal de-spreading and MRC, long code and short code generation for de-spreading, new finger allocation and finger timing adjustment.

Abstract: An access probe existing and generated within a base station to simulate a mobile terminal for the purpose of testing base station receive functionality within a communications system. The access probe data is injected at baseband rather than at RF to eliminate the need for analog/RF circuitry. The access probe performs injection at the front end of the base station receiver to exercise as much receive data path as possible. A unique ID is embedded in the access probes so that the communications system is aware which probes within a sequence were received successfully and at what power level. Within in-field applications, the unique ID allows the communications system to distinguish simulated access probes from those corresponding to real mobiles.

Abstract: A method and an apparatus for generating a chip of a chip sequence based on a supplied chip position index and a supplied sequence index is provided by generating a basic sequence bit using a portion of the chip position index and the sequence index, and by generating different mask bits using different portions of the chip position index and the sequence index, the mask bits being used in conjunction with the basic sequence bit to generate the chip. Such a chip generation process increases the chip generation rate so that users requesting chips to be generated may be efficiently pipelined.