Patents by Inventor Ganesh Upadhyaya

Ganesh Upadhyaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200328087
    Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
  • Patent number: 10734238
    Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 4, 2020
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
  • Publication number: 20200243326
    Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
  • Patent number: 10658174
    Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
  • Patent number: 10515815
    Abstract: Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 24, 2019
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Ganesh Upadhyaya, Yoshie Kimura, Weiye Zhu, Zhaohong Han, Seokhwan Lee, Noel Sun
  • Publication number: 20190157066
    Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
  • Publication number: 20190157095
    Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Inventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
  • Publication number: 20190157096
    Abstract: Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Inventors: Xiang Zhou, Ganesh Upadhyaya, Yoshie Kimura, Weiye Zhu, Zhaohong Han, Seokhwan Lee, Noel Sun
  • Patent number: 9466466
    Abstract: Methods, systems, and computer programs are presented for optimizing Critical Dimension Uniformity (CDU) during the processing of a substrate. One method includes identifying an operation of a recipe for processing a substrate within a chamber, the operation being configured to provide a pulsed radio frequency (RF) to the chamber. A plurality of tests are performed in the chamber for the operation utilizing the pulsed RF, each test having a duty cycle for the pulsed RF selected from a plurality of RF duty cycles. The method also includes for each test, measuring the critical dimension (CD) and the CDU for features in the substrate, and selecting a first duty cycle from the plurality of RF duty cycles based on the measured CDs and CDUs for the plurality of tests. The method also includes setting the selected first duty cycle in the operation of the recipe for processing the substrate.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 11, 2016
    Assignee: Lam Research Corporation
    Inventors: Qinghua Zhong, Ryan Martin, Ganesh Upadhyaya
  • Patent number: 9385003
    Abstract: Systems and methods for etching a substrate include arranging a substrate including a first structure and a dummy structure in a processing chamber. The first structure is made of a material selected from a group consisting of silicon dioxide and silicon nitride. The dummy structure is made of silicon. Carrier gas is supplied to the processing chamber. Nitrogen trifluoride and molecular hydrogen gas are supplied to the processing chamber. Plasma is generated in the processing chamber. The dummy structure is etched.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: July 5, 2016
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ming-Shu Kuo, Qinghua Zhong, Helene Del Puppo, Ganesh Upadhyaya, Gowri Kamarthy
  • Publication number: 20160049495
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 18, 2016
    Applicants: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina TREVINO, Yuan-Hung LIU, Gabriel Padron WELLS, Xing ZHANG, Hoong Shing WONG, Chang Ho MAENG, Taejoon HAN, Gowri KAMARTHY, Isabelle ORAIN, Ganesh UPADHYAYA
  • Patent number: 9252238
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 2, 2016
    Assignees: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina Trevino, Yuan-Hung Liu, Gabriel Padron Wells, Xing Zhang, Hoong Shing Wong, Chang Ho Maeng, Taejoon Han, Gowri Kamarthy, Isabelle Orain, Ganesh Upadhyaya
  • Patent number: 8431461
    Abstract: A method for forming devices with silicon gates over a substrate is provided. Silicon nitride spacers are formed on sides of the silicon gates. An ion implant is provided using the silicon nitride spacers as masks to form ion implant regions. A nonconformal layer is selectively deposited over the spacers and gates that selectively deposits a thicker layer on tops of the gates and spacers and between spacers than on sidewalls of the silicon nitride spacers. Sidewalls of the nonconformal layer are etched away on sidewalls of the silicon nitride spacers. The silicon nitride spacers are trimmed.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 30, 2013
    Assignee: Lam Research Corporation
    Inventors: Qinghua Zhong, Yoshie Kimura, Tae Won Kim, Qian Fu, Gladys Lo, Ganesh Upadhyaya, Yoko Yamaguchi