Abstract: A method of forming a microelectronic package, a microelectronic package formed according to the method, and a system including the microelectronic package. The method comprises: providing a die-substrate combination including: providing a die having die bumping sites thereon each including a layer comprising a stabilizing element; providing a substrate having substrate bumping sites thereon; before heating, placing a solder on at least one of the die bumping sites and the substrate bumping sites, the solder including a first solder element and a second solder element; and placing the die and the substrate in registration with one another to sandwich the solder therebetween. The method further comprises forming a plurality of joint structures including heating the die-substrate combination to reflow the solder.

Abstract: A microelectronic package, a substrate adapted to be used in forming the package, a method of forming the package, and a system including the package. The package includes a substrate; a die bonded to the substrate; a plurality of joint structures electrically bonding the die to the substrate. At least one of the plurality of joint structures comprises a layer including an alloy and intermetallic compound grains dispersed within the alloy, wherein: the alloy comprises a mixture of a first element and a second element both chosen such that a eutectic of the first element and second element has a melting temperature below a melting temperature of any element other than the eutectic in the at least one joint structure; and each of the intermetallic compound grains comprises a combination of the second element with a third element, wherein the third element is corrosion resistant.