Patents by Inventor Ganesh VENKATARAMANAN

Ganesh VENKATARAMANAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210005546
    Abstract: An electronic assembly (100) includes a mechanical carrier (102), a plurality of integrated circuits (104A, 104B) disposed on the mechanical carrier, a fan out package (108) disposed on the plurality of integrated circuits, a plurality of singulated substrates (112A, 112B) disposed on the fan out package, a plurality of electronic components (114A, 114B) disposed on the plurality of singulated substrates, and at least one stiffness ring (116A, 116B, 116C) disposed on the plurality of singulated substrates.
    Type: Application
    Filed: November 30, 2018
    Publication date: January 7, 2021
    Inventors: Mengzhi Pang, Shishuang Sun, Ganesh Venkataramanan
  • Publication number: 20200221568
    Abstract: A structure having embedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surf ace of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 9, 2020
    Inventors: Jin Zhao, Vijaykumar Krithivasan, Mengzhi Pang, Steven Wayne Butler, Ganesh Venkataramanan, Yang Sun
  • Patent number: 10241797
    Abstract: A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 26, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Mike Butler, Krishnan V. Ramani
  • Patent number: 9727340
    Abstract: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also include marking at least one second entry in the queue is ready to be picked for execution in response to at least one second tag associated with at least one second entry in the queue matching the first tag.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: August 8, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Achenbach, Teik Tan, Gregory W. Smaus, Ganesh Venkataramanan, Emil Talpes
  • Patent number: 9582286
    Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 28, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Debjit Das Sarma, Betty A. McDaniel, Gregory W. Smaus, Francesco Spadini
  • Patent number: 9489206
    Abstract: A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: November 8, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Francesco Spadini, Michael Achenbach, Emil Talpes, Ganesh Venkataramanan
  • Patent number: 9483273
    Abstract: A method includes suppressing execution of an operation portion of a load-operation instruction in a processor responsive to an invalid status of a load portion of load-operation instruction. A processor includes an instruction pipeline including an execution unit operable to execute instructions and a scheduler unit. The scheduler unit includes a scheduler queue and is operable to store a load-operation in the scheduler queue. The load-operation instruction includes a load portion and an operation portion. The scheduler unit schedules the load portion for execution in the execution unit, marks the operation portion in the scheduler queue as eligible for execution responsive to scheduling the load portion, receives an indication of an invalid status of the load portion, and suppresses execution of the operation portion responsive to the indication of the invalid status.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: November 1, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Francesco Spadini, Michael Achenbach, Emil Talpes, Ganesh Venkataramanan
  • Patent number: 9176738
    Abstract: Method and apparatus for fast decoding of microinstructions are disclosed. An integrated circuit is disclosed wherein microinstructions are queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a set of supported microinstructions. The execution unit receives microinstruction data including an operation code (opcode) or a complex opcode. The execution unit executes the microinstruction multiple times wherein the microinstruction is executed at least once to get an address value and at least once to get a result of an operation. The execution unit processes complex opcodes by utilizing both a load/store support and a simple opcode support by splitting the complex opcode into load/store and simple opcode components and creating an internal source/destination between the two components.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: November 3, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Emil Talpes
  • Patent number: 9170638
    Abstract: A method and apparatus are described for reducing power consumption in a processor. A micro-operation is selected for execution, and a destination physical register tag of the selected micro-operation is compared to a plurality of source physical register tags of micro-operations dependent upon the selected micro-operation. If there is a match between the destination physical register tag and one of the source physical register tags, a corresponding physical register file (PRF) read operation is disabled. The comparison may be performed by a wakeup content-addressable memory (CAM) of a scheduler. The wakeup CAM may send a read control signal to the PRF to disable the read operation. Disabling the corresponding PRF read operation may include shutting off power in the PRF and related logic.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: October 27, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Emil Talpes
  • Patent number: 8990623
    Abstract: Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: March 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Craig D. Eaton, Ganesh Venkataramanan, Srikanth Arekapudi
  • Publication number: 20150026686
    Abstract: A method includes suppressing execution of an operation portion of a load-operation instruction in a processor responsive to an invalid status of a load portion of load-operation instruction. A processor includes an instruction pipeline including an execution unit operable to execute instructions and a scheduler unit. The scheduler unit includes a scheduler queue and is operable to store a load-operation in the scheduler queue. The load-operation instruction includes a load portion and an operation portion. The scheduler unit schedules the load portion for execution in the execution unit, marks the operation portion in the scheduler queue as eligible for execution responsive to scheduling the load portion, receives an indication of an invalid status of the load portion, and suppresses execution of the operation portion responsive to the indication of the invalid status.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Francesco Spadini, Michael Achenbach, Emil Talpes, Ganesh Venkataramanan
  • Publication number: 20150026685
    Abstract: A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Francesco Spadini, Michael Achenbach, Emil Talpes, Ganesh Venkataramanan
  • Publication number: 20150026436
    Abstract: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also include marking at least one second entry in the queue is ready to be picked for execution in response to at least one second tag associated with at least one second entry in the queue matching the first tag.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael Achenbach, Teik Tan, Gregory W. Smaus, Ganesh Venkataramanan, Emil Talpes
  • Patent number: 8787058
    Abstract: A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 22, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Michael G. Butler, James Vinh
  • Publication number: 20140136819
    Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Debjit Das Sarma, Betty A. McDaniel, Gregory W. Smaus, Francesco Spadini
  • Patent number: 8656401
    Abstract: A method and processor are described for implementing programmable priority encoding to track relative age order of operations in a scheduler queue. The processor may comprise a scheduler queue configured to maintain an ancestry table including a plurality of consecutively numbered row entries and a plurality of consecutively numbered columns. Each row entry includes one bit in each of the columns. Pickers are configured to pick an operation that is ready for execution based on the age of the operation as designated by the ancestry table. The column number of each bit having a select logic value indicates an operation that is older than the operation associated with the number of the row entry that the bit resides in.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: February 18, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Srikanth Arekapudi, James Vinh, Mike Butler
  • Publication number: 20140025933
    Abstract: A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Mike Butler, Krishnan V. Ramani
  • Patent number: 8570783
    Abstract: Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: October 29, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Kyle S. Viau, James Vinh
  • Publication number: 20130117543
    Abstract: A method and apparatus for processing multi-cycle instructions include picking a multi-cycle instruction and directing the picked multi-cycle instruction to a pipeline. The pipeline includes a pipeline control configured to detect a latency and a repeat rate of the picked multi-cycle instruction and to count clock cycles based on the detected latency and the detected repeat rate. The method and apparatus further include detecting the repeat rate and the latency of the picked multi-cycle instruction, and counting clock cycles based on the detected repeat rate and the latency of the picked multi-cycle instruction.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 9, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ganesh Venkataramanan, Michael G. Butler
  • Publication number: 20130039109
    Abstract: A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 14, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ganesh Venkataramanan, Michael G. Butler, James Vinh