Patents by Inventor Ganesh Yerubandi

Ganesh Yerubandi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9831087
    Abstract: Provided is a split-gate embedded flash memory cell and method for forming the same. The flash memory cell includes split-gate transistors in which the control gate is aligned with respect to the floating gate without the use of a photolithographic patterning operation to pattern the material from which the control gates are formed. An anisotropic blanket etching operation is used to form the floating gates of the split-gate floating gate transistors alongside sidewalls of a sacrificial layer. Local oxidation of silicon (LOCOS) methods are not needed to form the inter-gate dielectric and therefore high integrity is maintained for the floating transistor gates. The floating transistor gates are formed of charge storage material such as silicon nitride, Si3N4 in some embodiments.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 28, 2017
    Assignee: WAFERTECH, LLC
    Inventors: Pang Leen Ong, Ganesh Yerubandi, Arjun Gupta
  • Publication number: 20170069501
    Abstract: Provided is a split-gate embedded flash memory cell and method for forming the same. The flash memory cell includes split-gate transistors in which the control gate is aligned with respect to the floating gate without the use of a photolithographic patterning operation to pattern the material from which the control gates are formed. An anisotropic blanket etching operation is used to form the floating gates of the split-gate floating gate transistors alongside sidewalls of a sacrificial layer. Local oxidation of silicon (LOCOS) methods are not needed to form the inter-gate dielectric and therefore high integrity is maintained for the floating transistor gates.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 9, 2017
    Inventors: Pang Leen ONG, Ganesh YERUBANDI, Arjun GUPTA
  • Patent number: 9035418
    Abstract: A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 19, 2015
    Assignee: WAFERTECH, LLC
    Inventors: Daniel Piper, Franklin Chiang, Ganesh Yerubandi
  • Publication number: 20130334652
    Abstract: A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.
    Type: Application
    Filed: August 19, 2013
    Publication date: December 19, 2013
    Applicant: WaferTech, LLC
    Inventors: Daniel Piper, Franklin Chiang, Ganesh Yerubandi
  • Patent number: 8530327
    Abstract: A shallow trench isolation (STI) structure and methods for forming the same provide an STI structure with a top surface formed completely of silicon nitride. The methods for forming the STI structures provide for at least one nitride deposition step followed by a further nitride deposition step to re-fill divots that occur along the upper portions of the trench sidewalls.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 10, 2013
    Assignee: Wafertech, LLC
    Inventors: Daniel Piper, Franklin Chiang, Ganesh Yerubandi
  • Publication number: 20130049161
    Abstract: A shallow trench isolation (STI) structure and methods for forming the same provide an STI structure with a top surface formed completely of silicon nitride. The methods for forming the STI structures provide for at least one nitride deposition step followed by a further nitride deposition step to re-fill divots that occur along the upper portions of the trench sidewalls.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: WAFERTECH, LLC
    Inventors: Daniel Piper, Franklin Chiang, Ganesh Yerubandi