Patents by Inventor Gang An

Gang An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222301
    Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Dingying Xu, Sairam Agraharam, Ashay Dani, Eric J. M. Moret, Tarek Ibrahim
  • Publication number: 20240222293
    Abstract: Technologies for ribbon field-effect transistors with variable fin numbers are disclosed. In an illustrative embodiment, a stack of semiconductor fins is formed, with each semiconductor fin having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor fins near the top of the stack can be removed. In other embodiments, one or more of the semiconductor fins at or closer to the bottom of the stack can be removed.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Kristof Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Siddharth Alur Narasimha Krishna, Sameer R. Paital, Helme A. Castro De la Torre
  • Publication number: 20240222124
    Abstract: A method for fabricating a semiconductor structure includes the following steps. Decomposing a layout to first connection patterns and second connection patterns alternatively arranged with each other, where a to-be-split pattern is disposed between the first connection pattern and the second connection pattern; splitting the to-be-split pattern into a cutting portion and a counterpart cutting portion; forming a first photomask having a layout constructed by the first connection pattern and the cutting portion; forming a second photomask having a layout constructed by the second connection pattern and the counterpart cutting portion; transferring layouts of the first and second photomasks to a target layer to form connection patterns and a merged pattern, where the contour of the merged pattern is defined by the cutting portion and the counterpart cutting portion, and each end surface of the merged pattern comprises a recessed region and a protruded region.
    Type: Application
    Filed: March 13, 2024
    Publication date: July 4, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Gang-Yi Lin, Yu-Cheng Tung, Yi-Wang Jhan, Yifei Yan, Xiaopei Fang
  • Publication number: 20240222257
    Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Ziyin Lin, Rahul N. Manepalli, Brandon C. Marin, Jeremy D. Ecton
  • Publication number: 20240219655
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Bai Nie, Brandon C. Marin, Dingying Xu, Gang Duan, Hongxia Feng, Jeremy D. Ecton, Kristof Darmawikarta, Kyle Jordan Arrington, Srinivas Venkata Ramanuja Pietambaram, Xiaoying Guo, Yiqun Bai, Ziyin Lin
  • Publication number: 20240215948
    Abstract: A medical scanning device used to scan a subject to be scanned, and obtain a medical image obtained by a current scan, and current scan-related information; and store the scan-related information in an identifiable medium, the identifiable medium being provided in a portable mobile carrier. The scan-related information is saved in the identifiable medium, and the identifiable medium is provided in the portable mobile carrier, so that the portable mobile carrier can be used to easily implement offline transfer of the scan-related information, and doctors can quickly and conveniently acquire the scan-related information so as to find a lesion or an issue of concern, thereby making medical scanning across devices, hospitals, cities, and countries simple and reducing costs.
    Type: Application
    Filed: December 15, 2023
    Publication date: July 4, 2024
    Inventors: Minyu Gu, Zhiwen Wang, Ke Tao, Gang Liu, Feng Wu, Weijie Zhang
  • Publication number: 20240224543
    Abstract: Multi-chip/die device including a logic IC die facing a first side of a glass substrate and a memory IC die facing, and coupled to, the logic IC die. First ones of first metallization features of the logic IC die are coupled to through-glass vias extending through a thickness of the glass substrate. The memory IC die is coupled to second ones of the first metallization features, either directly or by way of other through-glass vias. The logic IC die and/or memory IC die may be directly bonded to the through-glass vias or may be attached by solder. The logic IC die or memory IC die may be embedded within the glass substrate. Through-glass vias within a region beyond an edge of the memory IC die may couple the logic IC die to a host component either through a routing structure built up adjacent the memory IC die, or through solder features attached to the glass substrate adjacent to the memory IC die.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Suddhasattwa Nad, Gang Duan, Srinivas Pietambaram, Brandon Marin, Jeremy Ecton
  • Publication number: 20240222249
    Abstract: In one embodiment, an integrated circuit package substrate includes a glass layer having at least one roughened surface (e.g., with an average roughness above 100 nm) and a metal (e.g., a metal trace or metal via) in contact with the roughened surface of the glass layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Srinivas V. Pietambaram, Gang Duan, Brandon Christian Marin, Suddhasattwa Nad, Oladeji T. Fadayomi, Manuel Gadogbe, Matthew L. Tingey
  • Publication number: 20240219660
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Yiqun Bai, Dingying Xu, Eric J.M. Moret, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Bin Mu
  • Publication number: 20240222243
    Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240222216
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a die coupled to the package substrate by a plurality of interconnects. In an embodiment, a first layer is on the package substrate surrounding the die, and a second layer is over and around the die. In an embodiment, the second layer underfills the plurality of interconnects, and the second layer has a different material composition than the first layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Zhixin XIE, Jung Kyu HAN, Gang DUAN
  • Publication number: 20240222320
    Abstract: Multi-chip/die device including two or more substantially coplanar base IC dies directly bonded to a bridge IC die over or under the base IC dies. Direct bonding of the bridge IC die provides high pitch interconnect. A package metallization routing structure including conductive vias adjacent to the bridge IC die may be built up and terminate at first level interconnect interfaces. A temporary carrier, such as glass, may be employed to form such multi-chip devices.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Suddhasattwa Nad, Gang Duan, Srinivas Pietambaram, Brandon Marin, Jeremy Ecton
  • Publication number: 20240224374
    Abstract: Embodiments of the present disclosure relate to a method and apparatus of data transmission in a wireless communication system and a method and apparatus of receiving data in a wireless communication system. The method of data reception comprises transmitting a request for the RRC message to the network node based on default transmission parameters; and receiving the RRC message from the network node at a predetermined time unit. With embodiments of the present disclosure, it is possible to request the RRC message when the terminal device need this message and therefore the RRC message transmission can be reduced and in turn, the inter-node interference can be limited, and the number of LBTs required for these signal transmissions can be reduced if they are transmitted on unlicensed spectrum.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: NEC CORPORATION
    Inventors: Hongmei LIU, Lei JIANG, Gang WANG
  • Publication number: 20240215816
    Abstract: Methods, systems, and devices are provided for measuring eye refraction without a lens, and more particularly, for measuring eye refraction with a mobile device application. An exemplary method includes measuring a distance between a patient and a mobile device, presenting to the patient one or more visual targets sized and shaped to represent perfect vision such as by using Vernier targets or grating targets, instructing the patient to indicate whether the patient can accurately read the visual targets and, if not, to move closer to the mobile device until the patient can accurately read the visual targets, calculating a vision prescription for the patient based on the visual targets and a final distance between the patient and the mobile device, and displaying the vision prescription for the patient.
    Type: Application
    Filed: January 11, 2024
    Publication date: July 4, 2024
    Applicant: The Schepens Eye Research Institute, Inc.
    Inventor: Gang Luo
  • Publication number: 20240219633
    Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Suddhasattwa Nad, Brandon Marin, Jeremy Ecton, Gang Duan, Srinivas Pietambaram
  • Publication number: 20240222345
    Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Pietambaram, Gang Duan, Kyle Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240217216
    Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Kristof DARMAWIKARTA, Tarek A. IBRAHIM, Srinivas V. PIETAMBARAM, Dilan SENEVIRATNE, Jieying KONG, Thomas HEATON, Whitney BRYKS, Vinith BEJUGAM, Junxin WANG, Gang DUAN
  • Publication number: 20240220654
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for securely attributing a content platform while maintain user data privacy are described. In one aspect, a method includes receiving, by a content platform and from a first application executing on a client device, a request for digital components. The request includes a first anonymous token that includes a set of content. The content platform transmits, to the first application, a response including data for a digital component that includes content related to a second application and a hash value of the first anonymous token. The content platform receives, from the first application, a display notification indicating the display of the digital component via the application, the display notification including a second anonymous token and the hash value of the first anonymous token.
    Type: Application
    Filed: August 26, 2022
    Publication date: July 4, 2024
    Inventors: Gang WANG, Marcel M. Moti YUNG, Alex Daniel JACOBSON
  • Publication number: 20240222286
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a die layer, with a first side and a second side opposite from the first side. In an embodiment, the die layer comprises a first die, and a second die. In an embodiment, a bridge is on the first side of the die layer, where the bridge communicatively couples the first die to the second die. In an embodiment, electrically conductive routing is on the second side of the die layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Mohammad Mamunur RAHMAN, Brandon C. MARIN, Gang DUAN
  • Publication number: 20240219644
    Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Suddhasattwa Nad, Benjamin Duong, Hiroki Tanaka, Brandon Marin, Jeremy Ecton, Gang Duan, Srinivas Pietambaram, Hari Mahalingam