Abstract: A trench MOSFET sidewall structure includes a heavily doped substrate, a lightly doped epitaxial layer, a lightly doped well and a heavily doped source adjacent to one another to form a semiconductor substrate. Multiple trenches as well as multiple contact holes are defined in the substrate and each contact hole respectively is defined between two adjacent trenches. A top portion of the contact hole has a size larger than that of a bottom portion of the contact hole.

Abstract: The invention provides a casing structure for an electronic apparatus that achieves a thin size and light weight. The casing structure is capable of accommodating a display module, and comprises a sidewall and a bottom surface in which a conductive resin region and a nonconductive resin region are butt joined in a curved line. The casing structure of the electronic apparatus does not become thick due to the butt joining even when the joint portions are in a projection area of the display module. Furthermore, on the display side of the casing structure, there is no need to have special frame members for securing strength in addition to the display casing. The display casing accommodates and protects the display module from an external pressing force and also has a design function that the outer surface of the casing resembles that of an outer surface of a conventional notebook PC.

Abstract: A video bit stream with pictures comprising inter-coded content can be decoded upon receiving a channel start or file seek instruction. Pictures for beginning decoding and display of the bit stream can be selected based at least in part on one or more tuning parameters that set a preference between a latency of beginning to display video and possible defects in the displayed video. In some embodiments, to implement decoding upon a channel start or file seek, one or more types of data are generated for one or more pictures. For example, picture order counts are generated for pictures after a channel start or file seek operation. As another example, a decoder generates a frame number value that triggers re-initialization of a reference picture buffer before decoding after a channel start or file seek operation.

Abstract: Methods are disclosed for supporting stereo 3D video in computing devices. A computing device can receive stereo 3D video data employing a YUV color space and chroma subsampling, and can generate anaglyph video data therefrom. The anaglyph video data can be generated by unpacking the stereo 3D video data to left and right views and combining the left and right views into a single view via matrix transformation. The combining uses transform matrices that correspond to a video pipeline configuration. The transform matrix coefficients can depend on characteristics of the video pipeline components. Modified transform matrix coefficients can be used in response to changes in the video pipeline configuration. Video encoded in stereo 3D video data can be selected to be displayed in stereo 3D, anaglyph or monoscopic form, depending on user input and/or characteristics of video pipeline components.

Abstract: Described is an illumination structure suitable for a keyboard light of a portable computer. An example illumination structure includes a transparent acrylic board, a light source, and a light guide. The acrylic board may have a front surface and a rear surface, each of which is flat. The light source is provided at a tilt angle q at which an optical axis is almost at a critical angle with respect to the rear surface of the acrylic board. The light guide is located between the light source and the rear surface. Further, light rays radiated from the light source are refracted by the light guide and the optically-transparent panel, and travel towards the front surface, so as to illuminate the surface.

Abstract: Techniques and tools for reducing latency in video decoding for real-time communication applications that emphasize low delay. For example, a tool such as a video decoder selects a low-latency decoding mode. Based on the selected decoding mode, the tool adjusts output timing determination, picture boundary detection, number of pictures in flight and/or jitter buffer utilization. For low-latency decoding, the tool can use a frame count syntax element to set initial output delay for a decoded picture buffer, and the tool can use auxiliary delimiter syntax elements to detect picture boundaries. To further reduce delay in low-latency decoding, the tool can reduce number of pictures in flight for multi-threaded decoding and reduce or remove jitter buffers. The tool receives encoded data, performs decoding according to the selected decoding mode to reconstruct pictures, and outputs the pictures for display.

Abstract: A trench MOSFET with trench contact holes and a method for fabricating the same are disclosed. The MOSFET includes an N type substrate, an N type epitaxial layer on the substrate; a P well region on top of the epitaxial layer; a source region formed on the P well region; an oxide layer on the source region; a plurality of trenches which traverse the source region and the P well region and contact the epitaxial layer; a gate oxide layer and polysilicon formed in the trenches; a source contact hole and a gate contact hole, wherein the source contact hole and the gate contact hole have a titanium metal layer, a titanium nitride layer, and tungsten metal sequentially, respectively; a P+ implanted region; a source electrode formed above the source contact hole and a gate electrode formed above the gate contact hole.

Abstract: A video bit stream with pictures comprising inter-coded content can be decoded upon receiving a channel start or file seek instruction. Pictures for beginning decoding and display of the bit stream can be selected based at least in part on one or more tuning parameters that set a preference between a latency of beginning to display video and possible defects in the displayed video. In some embodiments, to implement decoding upon a channel start or file seek, one or more types of data are generated for one or more pictures. For example, picture order counts are generated for pictures after a channel start or file seek operation. As another example, a decoder generates a frame number value that triggers re-initialization of a reference picture buffer before decoding after a channel start or file seek operation.

Abstract: Adjustment of hardware acceleration level in a video decoder utilizing hardware acceleration is described. Errors are detected in a bitstream as it is decoded using different levels of error detection based on decoding characteristics. A statistical analysis is performed on the error values as they are detected. In one technique, if the bitstream is categorized as fitting a high error rate state in a bitstream model, then hardware acceleration is dropped. In another technique, error statistics based on run-lengths of good and bad bitstream units are kept, and compared to predetermined thresholds. If the thresholds are exceeded, the hardware acceleration level is dropped. The level is dropped in order to take advantage of superior error handing abilities of software-based decoding over hardware-accelerated decoding.

Abstract: A decoder which can detect errors in MPEG-2 coefficient blocks can identify syntactically-correct blocks which have out-of-bounds coefficients. The decoder computes coefficient bounds based on quantization scalers and quantization matrices and compares these to coefficient blocks during decoding; if a block has out-of-bounds coefficients, concealment is performed on the block. In a decoder implemented all in software, coefficient bounds checking is performed on iDCT coefficients against upper and lower bounds in a spatial domain. In a decoder which performs iDCT in hardware, DCT coefficients are compared to an upper energy bound.

Abstract: The invention provides a casing structure for an electronic apparatus that achieves a thin size and light weight. The casing structure is capable of accommodating a display module, and comprises a sidewall and a bottom surface in which a conductive resin region and a nonconductive resin region are butt joined in a curved line. The casing structure of the electronic apparatus does not become thick due to the butt joining even when the joint portions are in a projection area of the display module. Furthermore, on the display side of the casing structure, there is no need to have special frame members for securing strength in addition to the display casing. The display casing accommodates and protects the display module from an external pressing force and also has a design function that the outer surface of the casing resembles that of an outer surface of a conventional notebook PC.

Abstract: The invention broadly contemplates an electronic apparatus that provides improved antenna characteristics, while maintaining a thin size and light weight. The electronic apparatus of the present invention includes a display casing having a nonconductive resin region and a conductive resin region in a bottom surface thereof; a display module accommodated in the display casing; an antenna disposed in the nonconductive resin region; and a system casing accommodating a wireless module connected to the antenna. By disposing the antenna in the nonconductive resin region formed in the bottom surface of the display casing, it is possible to secure high radio wave sensitivity while preventing an antenna mounting portion from being exposed to the outside of the display casing. The casing structure of the electronic apparatus does not become thick because of butt joining even when the joint portions are in a projection area of an LCD module.