Patents by Inventor Gang Nie
Gang Nie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250112124Abstract: DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and below the IC die; and a gap within the dielectric material and extending around the metallization pattern.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Leonel Arana, Gang Duan, Benjamin Duong, Hongxia Feng, Tarek Ibrahim, Brandon C. Marin, Tchefor Ndukum, Bai Nie, Srinivas Pietambaram, Bohan Shan, Matthew Tingey
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Publication number: 20250112162Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.Type: ApplicationFiled: September 30, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Zheng Kang, Tchefor Ndukum, Yosuke Kanaoka, Jeremy Ecton, Gang Duan, Jefferson Kaplan, Yonggang Yong Li, Minglu Liu, Brandon C. Marin, Bai Nie, Srinivas Pietambaram, Shriya Seshadri, Bohan Shan, Deniz Turan, Vishal Bhimrao Zade
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Publication number: 20250112165Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Brandon Marin, Hiroki Tanaka, Robert May, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad, Numair Ahmed, Jeremy Ecton, Benjamin Taylor Duong, Bai Nie, Haobo Chen, Xiao Liu, Bohan Shan, Shruti Sharma, Mollie Stewart
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Publication number: 20250112175Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
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Patent number: 12253754Abstract: The embodiments of the present disclosure provide a display substrate, a display panel, and a display device. The display substrate includes: a first base substrate, wherein a plurality of sub-pixel regions arranged in an array are provided on the first base substrate; and a reflective layer provided on one side of the first base substrate, wherein a surface of the reflective layer away from the first base substrate is formed to include a plurality of first bumps and a plurality of second bumps, and the first bump has a size greater than that of the second bump.Type: GrantFiled: March 4, 2024Date of Patent: March 18, 2025Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jian Lin, Yong Zhang, Jian Wang, Wei Zhao, Gang Hua, Limin Zhang, Xianglei Qin, Zhichao Yang, Zepeng Sun, Yashuai An, Honggui Jin, Lingfang Nie, Zhilong Duan, Liangzhen Tang, Li Tian, Xinli Ma, Tianyu Xu, Bingyang Liu, Xueqiang Qian, Dongchuan Chen, Kaixuan Wang
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Publication number: 20250022786Abstract: Methods and apparatus for edge protected glass cores are disclosed herein. An example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.Type: ApplicationFiled: September 27, 2024Publication date: January 16, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Hiroki Tanaka, Haobo Chen, Brandon Christian Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jason Gamba, Bohan Shan, Robert May, Benjamin Taylor Duong, Bai Nie, Whitney Bryks
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Patent number: 11443550Abstract: A face recognition monitoring system based on spectrum and multi-band fusion, including a spectrum camera, a first module for acquiring a face spectral image, a second module for preprocessing data of the face spectral image, a face spectral image database and a third module for recognizing the face spectral image. The spectrum camera includes an optical lens and a silicon-based detector. The silicon-based detector includes a photoelectric conversion substrate and a filter film arranged thereon. The filter film includes N units each including a visible spectrum sensing area, a near-infrared spectral image sensing area and a RGGB image acquisition area. The N units cover all pixels on the photoelectric conversion substrate. A recognition method using the above system is also provided.Type: GrantFiled: December 20, 2021Date of Patent: September 13, 2022Assignee: Jilin QS Spectrum Data Technology Co. LtdInventors: Yu Ren, Gang Nie, Hao Zhou, Yuchen Liu, Xiaohui Liu, Shuo Wang, Yongsheng Zhang, Hongxing Cai, Zhihai Yao
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Publication number: 20220114834Abstract: A face recognition monitoring system based on spectrum and multi-band fusion, including a spectrum camera, a first module for acquiring a face spectral image, a second module for preprocessing data of the face spectral image, a face spectral image database and a third module for recognizing the face spectral image. The spectrum camera includes an optical lens and a silicon-based detector. The silicon-based detector includes a photoelectric conversion substrate and a filter film arranged thereon. The filter film includes N units each including a visible spectrum sensing area, a near-infrared spectral image sensing area and a RGGB image acquisition area. The N units cover all pixels on the photoelectric conversion substrate. A recognition method using the above system is also provided.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Yu REN, Gang NIE, Hao ZHOU, Yuchen LIU, Xiaohui LIU, Shuo WANG, Yongsheng ZHANG, Hongxing CAI, Zhihai YAO
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Publication number: 20210127712Abstract: Disclosed are Lactobacillus rhamnosus strain 753 and uses thereof, a silage additive and silage. Lactobacillus rhamnosus strain 753 is deposited in China General Microbiological Culture Collection Center with an accession number of CGMCC 18233. Lactobacillus rhamnosus strain 753 can improve the quality of silage in a high-temperature and high-humidity region, and the silage processed by Lactobacillus rhamnosus strain 753 has good stability and low pH, low aflatoxin B1 content and less dry matter loss. In addition, secondary fermentation can be avoided in the silage processed by Lactobacillus rhamnosus strain 753 when a silo or bale for silage is opened.Type: ApplicationFiled: October 31, 2020Publication date: May 6, 2021Applicant: SICHUAN AGRICULTURAL UNIVERSITYInventors: Xinquan ZHANG, Hao GUAN, Yanhong YAN, Yang SHUAI, Xiaoling LI, Qifan RAN, Gang NIE, Xia WANG, Ting HUANG, Dandan LI, Zhongfu YANG, Xiao MA, Linkai HUANG
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Patent number: 9774111Abstract: A cable assembly comprises a male connector plug, a circuit board and a cable. The circuit board has a first surface conductive layer and a second surface conductive layer that each include a plurality of front side pads and a plurality of rear side pads. The front side pads comprise four front side power pads soldered to four power terminals. The rear side pads comprise one rear side power pad and a soldering area of the rear side power pad is larger than a soldering area of the front side power pad. The circuit board is further at least provided with a first middle conductive layer positioned between the first surface conductive layer and the second surface conductive layer and a plurality of vias extending between layers.Type: GrantFiled: June 7, 2016Date of Patent: September 26, 2017Assignee: Molex, LLCInventors: Sheng Liang, Guang-Rong Xiao, You-Ai Li, Gang Nie
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Publication number: 20160365673Abstract: A cable assembly comprises a male connector plug, a circuit board and a cable. The circuit board has a first surface conductive layer and a second surface conductive layer that each include a plurality of front side pads and a plurality of rear side pads. The front side pads comprise four front side power pads soldered to four power terminals. The rear side pads comprise one rear side power pad and a soldering area of the rear side power pad is larger than a soldering area of the front side power pad. The circuit board is further at least provided with a first middle conductive layer positioned between the first surface conductive layer and the second surface conductive layer and a plurality of vias extending between layers.Type: ApplicationFiled: June 7, 2016Publication date: December 15, 2016Applicant: Molex, LLCInventors: Sheng LIANG, Guang-Rong XIAO, You-Ai LI, Gang NIE
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Publication number: 20060223591Abstract: A communications device (100) and method (300) for selectively answering an incoming call received by the communications device (100). The method (100) provides an alert signal (330) in response to receiving; the incoming call (310) and then provides for automatically answering the incoming call (360) when the device detects (355) a change in state from an inoperative coupling state to an operative coupling state between the device (100) and an earpiece and microphone accessory (210).Type: ApplicationFiled: March 23, 2006Publication date: October 5, 2006Inventors: Guo Wang, Jin Lu, Gang Nie
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Patent number: D984966Type: GrantFiled: May 11, 2021Date of Patent: May 2, 2023Assignee: Molex, LLCInventors: Ravikanth Desai, Narayan Mithun, Kalidindi Ramesh Raju, Debashis Sarkar, Rahul Bhaskar, Gang Nie
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Patent number: D985499Type: GrantFiled: May 11, 2021Date of Patent: May 9, 2023Assignee: Molex, LLCInventors: Ravikanth Desai, Narayan Mithun, Kalidindi Ramesh Raju, Debashis Sarkar, Rahul Bhaskar, Gang Nie
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Patent number: D993924Type: GrantFiled: May 11, 2021Date of Patent: August 1, 2023Assignee: Molex, LLCInventors: Ravikanth Desai, Narayan Mithun, Kalidindi Ramesh Raju, Debashis Sarkar, Rahul Bhaskar, Gang Nie
