Abstract: A transmitting device is configured to generate a first encoded symbol and a second encoded symbol by encoding a first burst and a second burst, respectively. The transmitting device is configured to generate a first transmitting symbol and a second transmitting symbol by selectively inverting the first and second encoded symbols on the basis of a logic level of a bit with a specific sequence number of each of a previously generated transmitting symbol and the first burst.

Abstract: An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.

Abstract: A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.

Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Abstract: An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.

Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.

Abstract: A semiconductor apparatus including: a peripheral circuit region and a memory region including a plurality of unit memory blocks coupled to the peripheral circuit region through data lines and control signal lines. The control signal lines having a path configuration configured to equalize a value corresponding to a difference between times required for transferring data from the peripheral circuit region to the plurality of unit memory blocks with another value corresponding to a difference between times required for transferring control signals related to data input/output from the peripheral circuit region to the plurality of unit memory blocks to substantially a same value.

Abstract: A semiconductor apparatus includes a voltage divider, a plurality of reference voltage controllers, and a plurality of receivers. The voltage divider outputs a plurality of division voltages. Each of the plurality of reference voltage controllers is configured to receive in common the plurality of division voltages. Each of the plurality of receivers is configured to receive data by utilizing at least one reference voltage. The plurality of reference voltage controllers are coupled to the plurality of receivers in a one-to-one manner, and each of the plurality of reference voltage controllers is configured to select at least one division voltage among the plurality of division voltages and provide the one division voltage as the at least one reference voltage to a corresponding receiver among the plurality of receivers.

Abstract: A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. Wherein, the storage circuit stores the fuse data and outputs it as a storage signal and the parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal, the fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal, the error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.

Abstract: A semiconductor apparatus includes a voltage divider, a plurality of reference voltage controllers, and a plurality of receivers. The voltage divider outputs a plurality of division voltages. Each of the plurality of reference voltage controllers is configured to receive in common the plurality of division voltages. Each of the plurality of receivers is configured to receive data by utilizing at least one reference voltage. The plurality of reference voltage controllers are coupled to the plurality of receivers in a one-to-one manner, and each of the plurality of reference voltage controllers is configured to select at least one division voltage among the plurality of division voltages and provide the one division voltage as the at least one reference voltage to a corresponding receiver among the plurality of receivers.

Abstract: A semiconductor apparatus including: a peripheral circuit region and a memory region including a plurality of unit memory blocks coupled to the peripheral circuit region through data lines and control signal lines. The control signal lines having a path configuration configured to equalize a value corresponding to a difference between times required for transferring data from the peripheral circuit region to the plurality of unit memory blocks with another value corresponding to a difference between times required for transferring control signals related to data input/output from the peripheral circuit region to the plurality of unit memory blocks to substantially a same value.

Abstract: A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. The storage circuit stores the fuse data and outputs it as a storage signal. The parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal. The fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal. The error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.

Abstract: A semiconductor apparatus may include a fuse circuit, registers, and an error correction circuit. The fuse circuit may be configured to generate a first fuse array signal and a second fuse array signal based on external repair information. The registers may be configured to store the first and second fuse array signals, and output stored signals as first fuse information and second fuse information. The error correction circuit may be configured to generate error correction information based on the first fuse information and the second fuse information.