Abstract: An ear apparatus may comprise one or more of a housing, an electrode, a biometric sensor, a speaker driver, and/or other components. The housing of the ear apparatus may be configured to be attached to an ear. The electrode may be carried by the housing. The electrode may be configured to measure an electrical signal from the ear. The electrical signal may include a reference signal, a ground signal, or a bias signal. The biometric sensor may be carried by the housing. The biometric sensor may be configured to measure one or more biometric characteristics from the ear. The speaker driver may be carried by the housing. The speaker driver may be configured to produce sound.

Abstract: In one aspect, an apparatus includes: a first feedback digital-to-analog converter (DAC) to receive a first feedback signal from a first successive approximation register (SAR) and output a first analog signal; a comparator to compare the first analog signal with a reference voltage; the first SAR to store a digital value based on the comparison and provide the first feedback signal to the first DAC; a second feedback DAC to receive a modulated quantized residual error based on the comparison and output a second analog signal; a second SAR to store a quantized residual error; and a delta-sigma modulator (DSM) to modulate the quantized residual error and provide the modulated quantized residual error to the second feedback DAC.

Abstract: Positive and negative glitch detectors detect glitches on a supply voltage node. The positive glitch detector has a capacitor and a resistor serially coupled between the supply voltage node and ground. An amplifier is coupled to a first node between the capacitor and resistor. A positive glitch results in the glitch on the first node (normally biased low) and generation of a clock pulse by the amplifier that causes a latch to assert its output to indicate the positive glitch. The negative glitch detector has a capacitor and resistor coupled in parallel between the supply voltage node and a second node. A negative glitch on the supply voltage node decreases the voltage on the second node (normally biased high) and an inverting amplifier coupled to the second node generates a clock pulse to cause a latch to assert its output to indicate the negative voltage glitch.

Abstract: A circuit board with embedded resistors and a method for fabricating the same are provided. The circuit board includes the circuit substrate and the variable resistor region. The variable resistor region includes the first resistor layer, the second resistor layer and the liquid metal material. The first resistor layer is electrically connected to the circuit substrate, and the second resistor layer overlaps the first resistor layer. The liquid metal material is located on and is electrically connected to the first resistor layer. The liquid metal material is spaced from the second resistor layer without any electrical connection under the initial temperature. The liquid metal material is electrically connected to the second resistor layer under the first temperature which is higher than the initial temperature.

Abstract: A flexible circuit board and a method of fabricating the same are provided. The flexible circuit board includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a signal layer disposed within the second dielectric layer, a third dielectric layer disposed on the second dielectric layer, and liquid metal composites. The signal layer includes a trace and a pad. The liquid metal composites are disposed to surround the trace, but not enclose the pad, thereby satisfying requirements of the signal layer for great bending numbers and high frequency signal transmission.

Abstract: In one embodiment, an apparatus includes: a replica sampler circuit to sample a first voltage that is based on a reference voltage, the replica sampler circuit to at least approximate a non-linearity of a bias generator. The replica sampler circuit may include: a switch circuit, when enabled, to pass the first voltage; and a capacitor coupled to the switch circuit, the capacitor to be charged by the first voltage. The apparatus also may include a comparator coupled to the replica sampler circuit, the comparator having a first input terminal to receive the sampled first voltage and a second input terminal to receive the reference voltage, where the comparator is to output a first signal having a first value when the sampled first voltage departs from the reference voltage by at least a threshold amount, to cause a refresh of at least a portion of the bias generator.

Abstract: A multi-layer headgear system may comprise one or more of a head-mounted display adapter plate, a headgear frame, a sensor-engagement assembly, and/or other components. A first side of the head-mounted display adapter plate may be configured to be attached to a head-mounted display. A second side of the head-mounted display adapter plate may be configured to be attached to a first side of the headgear frame. A first side of the sensor-engagement assembly may be configured to be attached to a second side of the headgear frame. The sensor-engagement assembly may be configured to position one or more sensors with respect to a face.

Abstract: A circuit board and a manufacturing method therefor. The circuit board includes a substrate and a plurality of traces arranged at intervals on the substrate. Each trace includes a seed layer located on one surface of the substrate, a first copper layer located on the surface of the seed layer away from the substrate, and a second copper layer plated on one surface of the substrate. The second copper layer covers the seed layer and the first copper layer. The ratio of the thickness of each trace to the space between any two adjacent traces is greater than 1. The thickness of the second copper layer in the thickness direction of the substrate is greater than the thickness of the second copper layer in a direction perpendicular to the thickness direction of the substrate.

Abstract: A circuit board includes an inner wiring substrate and a first side plate. The inner wiring substrate includes a plurality of first connection pads at a side. The first side plate is disposed on the inner wiring substrate and defines a plurality of first holes exposing the first connection pads. Each first hole includes a first end facing the first connection pad and a second end facing away from the first connection pad. A central distance between two adjacent first connection pads is greater than a center distance between two second ends of two adjacent first holes. The first holes are filled with first conductive bodies, each first conductive body is electrically connected to the first connection pad and extends out of the first hole to form a connection portion. A method for manufacturing the circuit board and a display module are also disclosed.

Abstract: A multi-layer headgear system may comprise one or more of a head-mounted display adapter plate, a headgear frame, a sensor-engagement assembly, and/or other components. A first side of the head-mounted display adapter plate may be configured to be attached to a head-mounted display. A second side of the head-mounted display adapter plate may be configured to be attached to a first side of the headgear frame. A first side of the sensor-engagement assembly may be configured to be attached to a second side of the headgear frame. The sensor-engagement assembly may be configured to position one or more sensors with respect to a face.

Abstract: This application provides a method for training a semantic understanding model, including: obtaining a first training sample set; performing denoising processing on the first training sample set to form a corresponding second training sample set; processing the second training sample set by using a semantic understanding model, to determine initial parameters of the semantic understanding model; processing the second training sample set by using the semantic understanding model in response to the initial parameters of the semantic understanding model, to determine update parameters of the semantic understanding model; and iteratively updating a semantic representation layer network parameter and a task-related output layer network parameter of the semantic understanding model by using the second training sample set and according to the update parameters of the semantic understanding model.

Abstract: An ear apparatus may comprise one or more of a housing, an electrode, a biometric sensor, a speaker driver, and/or other components. The housing of the ear apparatus may be configured to be attached to an ear. The electrode may be carried by the housing. The electrode may be configured to measure an electrical signal from the ear. The electrical signal may include a reference signal, a ground signal, or a bias signal. The biometric sensor may be carried by the housing. The biometric sensor may be configured to measure one or more biometric characteristics from the ear. The speaker driver may be carried by the housing. The speaker driver may be configured to produce sound.

Abstract: An ear apparatus may comprise one or more of a housing, an electrode, a biometric sensor, a speaker driver, and/or other components. The housing of the ear apparatus may be configured to be attached to an ear. The electrode may be carried by the housing. The electrode may be configured to measure an electrical signal from the ear. The electrical signal may include a reference signal, a ground signal, or a bias signal. The biometric sensor may be carried by the housing. The biometric sensor may be configured to measure one or more biometric characteristics from the ear. The speaker driver may be carried by the housing. The speaker driver may be configured to produce sound.

Abstract: A phase-change memory (PCM) device includes a first electrode, a second electrode, a memory layer, and a heater. The memory layer includes a phase-change material and is electrically coupled between the first electrode and the second electrode. The heater is arranged near the memory layer and is configured to heat a programming region of the memory layer in response to an electric current that passes through the heater. The heater is coupled to a power source via an electric current path that does not pass through the memory layer.

Abstract: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.

Abstract: A circuit board and a manufacturing method therefor. The circuit board includes a substrate and a plurality of traces arranged at intervals on the substrate. Each trace includes a seed layer located on one surface of the substrate, a first copper layer located on the surface of the seed layer away from the substrate, and a second copper layer plated on one surface of the substrate. The second copper layer covers the seed layer and the first copper layer. The ratio of the thickness of each trace to the space between any two adjacent traces is greater than 1. The thickness of the second copper layer in the thickness direction of the substrate is greater than the thickness of the second copper layer in a direction perpendicular to the thickness direction of the substrate.

Abstract: This application provides a method for training a semantic understanding model, including: obtaining a first training sample set; performing denoising processing on the first training sample set to form a corresponding second training sample set; processing the second training sample set by using a semantic understanding model, to determine initial parameters of the semantic understanding model; processing the second training sample set by using the semantic understanding model in response to the initial parameters of the semantic understanding model, to determine update parameters of the semantic understanding model; and iteratively updating a semantic representation layer network parameter and a task-related output layer network parameter of the semantic understanding model by using the second training sample set and according to the update parameters of the semantic understanding model.

Abstract: A magnetic memory device includes a core element, a free layer surrounding the core element, a barrier layer surrounding the free layer, and a reference layer surrounding the barrier layer. Two ends of the core element are electrically coupled to a first electrode and a second electrode, respectively. A direction of magnetization of the free layer is switchable between a first direction and a second direction under an influence of an electrical current flowing along the core element. The barrier layer includes an electrically insulating material. The reference layer is electrically coupled to a third electrode. A direction of magnetization of the reference layer remains along the first direction or the second direction.

Abstract: A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.