Abstract: Implementations of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In some implementations, the disclosed 3D memory device comprises: a stack structure including a plurality of dielectric layers and conductive layers alternatively stacked in a vertical direction; an array of channel structures each vertically penetrating the stack structure, each channel structure including a functional layer and a channel layer; and a plurality of isolation structures extending in parallel along a first lateral direction and vertically in an upper portion of the stack structure, each isolation structure being in contact with the channel layers of two adjacent rows of channel structures.

Abstract: A semiconductor device includes a stack comprising interleaved conductive layers and dielectric layers stacked along a first direction, and a contact structure extending through the stack along the first direction. The conductive layers include a first conductive layer and a second conductive layer under the first conductive layer, and the first conductive layer is in contact with the contact structure. The first conductive layer includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness in contact with the contact structure.

Abstract: An unlocking method and an intelligent lock based on vein input and identification. The method includes steps of obtaining positional information of a target part, adjusting a position of the target part to be within a preset position-identification range, inputting a vein image of the target part to be within the position-identification range, where the vein image includes a first vein image and a second vein image; processing the input first vein image to obtain a first vein feature of the first vein image, constructing a feature map based on the first vein feature; processing the input second vein image to obtain a second vein feature of the second vein image, comparing the second vein feature with the first vein feature of the feature map to obtain a comparison result, and determining an unlocking state based on the comparison result.

Abstract: The memory cell includes: an array of channel layers including N channel layers vertically provided on a substrate, a tunneling layer and a memory layer being sequentially provided on an outer side of the channel layers; N thermal conductive cores provided in the N channel layers respectively and penetrating the substrate; and an array of thermocouples including a thermocouple word line layer grown on the substrate and N thermocouple layers on the thermocouple word line layer, the thermocouple layers being connected one-to-one with the thermal conductive cores. A first potential difference is applied between the thermocouple word line layer and the thermocouple layer, and the thermal conductive core connected with the thermocouple layer is heated, so that the channel layer and the memory layer corresponding to the thermal conductive core are maintained at first and second preset temperatures respectively under a thermal insulation effect of the tunneling layer.

Abstract: Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and/or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and/or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.

Abstract: A system and multiple hardware structures to provide secure, anti-disassembly, anti-tamper and uninterrupted network connection between laptop computer and wireless networks. An anti-disassembly structure may include a locking arm having a rear end fixed to a side of a plug, and a front end having an outwardly biased latch projection. When the plug is inserted into a socket, the locking arm inserts into a corresponding slot on a side of the socket. A front end of the locking arm may be bent inward, and the latch projection may extend into a lock hole on the side of the slot to complete the locking. Additional protective and tamper resistant features may be included, such as anti-assembly screws, waterproofing, and protective enclosures with shock resistance.

Abstract: A production line for producing components to a high standard of cleanliness and sealed and protected in that state includes a loading device, a cleaning device, a detecting device, a pasting device, a heat-sealing device, a packing device, and transfer devices of the production line. The production line automatically processes the components for obtaining components with the high cleanliness. By the processes of protective film pasting, heat-sealing, and packing, the components may be further protected from subsequent pollution. A method for producing components with a high cleanliness applied to the production line is also disclosed.

Abstract: A multilayer film having enhanced toughness and optical properties is provided. The multilayer film includes a base layer, an outer layer, and a tie layer between the base layer and the outer layer. The multilayer film can also include additional layers. Methods for making such multilayer films are also provided. Multilayer films according to the present invention are particularly useful packaging applications where rupture resistance and high clarity are desirable.

Abstract: A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.

Abstract: Compositions comprising a mixture of a polymer recyclate and a compatibilizer are provided. The polymer recyclate comprises a first low polarity polymer having an oxygen vapor transmission rate (OVTR) greater than or equal to 800 cc·?m/m2·day·atm and a high polarity polymer, comprising at least one polar monomer and having an OVTR less than or equal to 200 cc·?m/m2·day·atm. The compatibilizer comprises a second low polarity polymer grafted with one or more functional groups. The mixture is subjected to compounding conditions to form a polymer product having a dispersed phase of domains of the high polarity polymer in a matrix phase of the first low polarity polymer. Methods for producing such compositions by recycling barrier films are also provided, wherein the barrier film comprises at least one layer of the first low polarity polymer and at least one layer comprising the high polarity polymer, as described above.

Abstract: A carbon nanotube composite structure includes a carbon nanotube and a film-like structure. The carbon nanotube includes a p-type portion and an n-type portion. The film-like structure is a molybdenum disulfide film or a tungsten disulfide film, and the film-like structure covers the n-type portion.

Abstract: Provided is an L-shaped stepped word line structure including: L-shaped word line units, each including a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction. A word line terminal included in the short side is formed in a stepped stacked layer structure including stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region including a short side region surface/internal metal layer respectively located on a surface/in an interior. In a first direction, a length of the short side region surface metal layer is greater than that of the short side region internal metal layer, and the word line terminal corresponds to the short side region surface metal layer.

Abstract: A method of determining an image feature, an electronic device, and a storage medium are provided, which relate to the field of artificial intelligence technology, in particular to fields of computer vision and depth learning technology, and may be applied to scenarios such as image processing and image recognition. The method includes: dividing an original image into a plurality of local images as an image to be processed, and each local image includes a plurality of image blocks; determining a local feature of the image to be processed according to a relationship between each image block in each local image; and determining a global feature of the image to be processed according to a relationship between a first image block at a preset position in a local image and one or more second image blocks at the preset position in other local images of the plurality of local images.

Abstract: A method of fusing an image feature, an electronic device, and a storage medium are provided, which relate to the field of artificial intelligence, in particular to fields of computer vision and depth learning, and may be applied to scenarios such as image processing and image recognition. The method includes: inputting an image into a first image processing model among N serially connected image processing models, to obtain an output feature of the first image processing model, an i-th image processing model includes a first shared layer to an i-th shared layer, i=1, . . . , N, and N is a natural number greater than or equal to 2; inputting an output feature of a j-th image processing model into a (j+1)-th image processing model, to obtain an output feature of the (j+1)-th image processing model, j=1, . . . , N?1; and fusing the output features of the N image processing models.

Abstract: A PV unit for use on a body of water includes a module array including at least one PV module and an array holder designed to move the module array between an operating position on a surface of the body of water and a submerged position below the surface of the body of water. The array holder includes fixing means for coupling to a bottom and/or to the surface of the body of water. The module array is movable in a direction relative to the array holder.

Abstract: A driving assistance device includes a visibility determination unit that determines whether visual recognition within a predetermined distance from a vehicle can be achieved in a traveling direction of the vehicle, an operation detection unit that detects an operation of causing the vehicle to enter a space in which an oncoming vehicle travels, based on information representing an operation of the vehicle by a driver, and a control warning unit that warns the driver or controls the vehicle in such a way that the vehicle does not enter the space when the visibility determination unit determines that visual recognition within the predetermined distance cannot be achieved, and the operation detection unit detects the operation of causing the vehicle to enter the space.

Abstract: The present disclosure discloses a method and apparatus for generating an image. A specific embodiment of the method comprises: acquiring at least two frames of facial images extracted from a target video; and inputting the at least two frames of facial images into a pre-trained generative model to generate a single facial image. The generative model updates a model parameter using a loss function in a training process, and the loss function is determined based on a probability of the single facial generative image being a real facial image and a similarity between the single facial generative image and a standard facial image. According to this embodiment, authenticity of the single facial image generated by the generative model may be enhanced, and then a quality of a facial image obtained based on the video is improved.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a carbon nanotube structure, a source electrode and a drain electrode. The gate insulating layer is located on the gate electrode. The carbon nanotube structure is located on the gate insulating layer. The source electrode and the drain electrode are arranged at intervals and electrically connected to the carbon nanotube structure respectively. The thin film transistor further includes an interface charge layer, and the interface charge layer is located between the carbon nanotube structure and the gate insulating layer.

Abstract: A computer device includes a processor; a memory connected to the processor, where the memory includes a first memory region; and a plurality of network adapters connected to the processor. The processor is configured to: when registering the first memory region with the plurality of network adapters, record a first memory address in a first memory address translation table (MTT) into a memory protection table (MPT) of each network adapter in the plurality of network adapters, so that each of the network adapters is capable of accessing the first memory region by using the first memory address translation table. The first memory address translation table is used to indicate a correspondence between a virtual address of the first memory region and a physical address of the first memory region.