Patents by Inventor Gang Zhang

Gang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12338997
    Abstract: An apparatus capable of monitoring and adjusting an in-furnace combustion condition in real time, having: a furnace having a heating chamber, a combustor, a charging door, an exhaust gas flow port, and an exhaust gas flow pipe, wherein the combustor is used for introducing fuel and/or an oxygen-containing gas into the heating chamber to form a flame, the charging door is used for adding a raw material, and the gas generated by combustion in the heating chamber enters the exhaust gas flow pipe through the exhaust gas flow port; two sensors of the same type arranged at different positions in the exhaust gas flow pipe; and a control device receiving signals of the two sensors and adjusting, according to a difference between the signals, the amount of the fuel and/or the oxygen-containing gas entering the combustor.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: June 24, 2025
    Assignee: L'Air Liquide, Societe Anonyme Pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Peter Van Kampen, Yuejin Pan, Gang Zhang, Wenbiao Zhou
  • Patent number: 12336204
    Abstract: A tunneling transistor includes a gate, an insulating layer placed on the gate, a carbon nanotube being semiconducting, a film-like structure, a source electrode, and a drain electrode. The carbon nanotube is placed on a surface of the insulating layer away from the gate. The film-like structure covers a portion of the carbon nanotube, and the film-like structure is a molybdenum disulfide film or a tungsten disulfide film. The source electrode is electrically connected to the film-like structure. The drain electrode is electrically connected to the carbon nanotube.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: June 17, 2025
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Gao-Tian Lu, Yang Wei, Shou-Shan Fan, Yue-Gang Zhang
  • Publication number: 20250159883
    Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The disclosed semiconductor device can comprise a stack structure comprising alternative conductive layers and dielectric layers, and a gate line structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory fingers. The gate line structure can comprise gate line slit structure segments aligned along the first lateral direction, and at least one first dummy contact structure located between adjacent gate line slit structure segments in the first lateral direction.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 15, 2025
    Inventors: Kuan Dong, Meng Xiao, Zhou He, Longdong Liu, Xianghui Zhao, Gang Zhang
  • Publication number: 20250159884
    Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed semiconductor device comprises a stack structure comprising alternative conductive layers and dielectric layers, and a gate line structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks. The gate line structure comprises gate line slit structure segments aligned along the first lateral direction, and at least one dummy channel structure located between the gate line slit structure segments in the first lateral direction.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 15, 2025
    Inventors: Zhou He, Meng Xiao, Longdong Liu, Kuan Dong, Gang Zhang
  • Publication number: 20250159894
    Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. One disclosed semiconductor device comprises a stack structure comprising an array region and a contact region, and a gate line slit structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks. The gate line slit structure comprises a first dummy channel structure located at a boundary between the array region and the contact region, a first gate line slit segment extending laterally from the first dummy channel structure into the array region, and a second gate line slit segment extending laterally from the first dummy channel structure into the contact region.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 15, 2025
    Inventors: Zhou He, Meng Xiao, Kuan Dong, Longdong Liu, Gang Zhang
  • Publication number: 20250142817
    Abstract: Implementations of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In some implementations, the disclosed 3D memory device comprises: a stack structure including a plurality of dielectric layers and conductive layers alternatively stacked in a vertical direction; an array of channel structures each vertically penetrating the stack structure, each channel structure including a functional layer and a channel layer; and a plurality of isolation structures extending in parallel along a first lateral direction and vertically in an upper portion of the stack structure, each isolation structure being in contact with the channel layers of two adjacent rows of channel structures.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 1, 2025
    Inventors: Kuan Dong, Gang Zhang, Meng Xiao, Longdong Liu, Zhou He, Pan Wang, Jin Dong, Meng Xiao, Liheng Liu
  • Publication number: 20250105149
    Abstract: A semiconductor device includes a stack comprising interleaved conductive layers and dielectric layers stacked along a first direction, and a contact structure extending through the stack along the first direction. The conductive layers include a first conductive layer and a second conductive layer under the first conductive layer, and the first conductive layer is in contact with the contact structure. The first conductive layer includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness in contact with the contact structure.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 27, 2025
    Inventors: Meng Xiao, Kuan Dong, Longdong Liu, Zhou He, Xianghui Zhao, Zuixin Zeng, Gang Zhang
  • Publication number: 20250057474
    Abstract: An unlocking method and an intelligent lock based on vein input and identification. The method includes steps of obtaining positional information of a target part, adjusting a position of the target part to be within a preset position-identification range, inputting a vein image of the target part to be within the position-identification range, where the vein image includes a first vein image and a second vein image; processing the input first vein image to obtain a first vein feature of the first vein image, constructing a feature map based on the first vein feature; processing the input second vein image to obtain a second vein feature of the second vein image, comparing the second vein feature with the first vein feature of the feature map to obtain a comparison result, and determining an unlocking state based on the comparison result.
    Type: Application
    Filed: February 2, 2024
    Publication date: February 20, 2025
    Applicant: IDLESPACE TECHNOLOGY COMPANY CO., LTD
    Inventors: Gang ZHANG, Qiyun SU, Xian LI
  • Publication number: 20240421769
    Abstract: Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and/or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and/or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Omar E. Elaasar, Shan He, Gang Zhang, Anandaroop Chakrabarti
  • Publication number: 20240421032
    Abstract: The memory cell includes: an array of channel layers including N channel layers vertically provided on a substrate, a tunneling layer and a memory layer being sequentially provided on an outer side of the channel layers; N thermal conductive cores provided in the N channel layers respectively and penetrating the substrate; and an array of thermocouples including a thermocouple word line layer grown on the substrate and N thermocouple layers on the thermocouple word line layer, the thermocouple layers being connected one-to-one with the thermal conductive cores. A first potential difference is applied between the thermocouple word line layer and the thermocouple layer, and the thermal conductive core connected with the thermocouple layer is heated, so that the channel layer and the memory layer corresponding to the thermal conductive core are maintained at first and second preset temperatures respectively under a thermal insulation effect of the tunneling layer.
    Type: Application
    Filed: November 2, 2021
    Publication date: December 19, 2024
    Inventors: Gang ZHANG, Chunlong LI, Zongliang HUO, Tianchun YE
  • Publication number: 20240385653
    Abstract: A system and multiple hardware structures to provide secure, anti-disassembly, anti-tamper and uninterrupted network connection between laptop computer and wireless networks. An anti-disassembly structure may include a locking arm having a rear end fixed to a side of a plug, and a front end having an outwardly biased latch projection. When the plug is inserted into a socket, the locking arm inserts into a corresponding slot on a side of the socket. A front end of the locking arm may be bent inward, and the latch projection may extend into a lock hole on the side of the slot to complete the locking. Additional protective and tamper resistant features may be included, such as anti-assembly screws, waterproofing, and protective enclosures with shock resistance.
    Type: Application
    Filed: May 16, 2024
    Publication date: November 21, 2024
    Inventors: Chang-Gang ZHANG, Xiaotian WU
  • Patent number: 12122088
    Abstract: A production line for producing components to a high standard of cleanliness and sealed and protected in that state includes a loading device, a cleaning device, a detecting device, a pasting device, a heat-sealing device, a packing device, and transfer devices of the production line. The production line automatically processes the components for obtaining components with the high cleanliness. By the processes of protective film pasting, heat-sealing, and packing, the components may be further protected from subsequent pollution. A method for producing components with a high cleanliness applied to the production line is also disclosed.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 22, 2024
    Assignee: Fulian Yuzhan Precision Technology Co., Ltd
    Inventors: Jian-Wen Gao, Ting-Ting Li, Chu-Hui Wu, Ai-Jun Tang, Hui Wang, Shi Chen, Bo Yang, Feng Zhang, Kun-Liang Lin, Jian-Gang Zhang
  • Patent number: 12122945
    Abstract: A multilayer film having enhanced toughness and optical properties is provided. The multilayer film includes a base layer, an outer layer, and a tie layer between the base layer and the outer layer. The multilayer film can also include additional layers. Methods for making such multilayer films are also provided. Multilayer films according to the present invention are particularly useful packaging applications where rupture resistance and high clarity are desirable.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 22, 2024
    Assignee: Equistar Chemicals, LP
    Inventors: Mick C. Hundley, Gang Zhang, William R. Podborny
  • Patent number: 12120875
    Abstract: A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 15, 2024
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Gang Zhang, Zongliang Huo
  • Publication number: 20240336769
    Abstract: Compositions comprising a mixture of a polymer recyclate and a compatibilizer are provided. The polymer recyclate comprises a first low polarity polymer having an oxygen vapor transmission rate (OVTR) greater than or equal to 800 cc·?m/m2·day·atm and a high polarity polymer, comprising at least one polar monomer and having an OVTR less than or equal to 200 cc·?m/m2·day·atm. The compatibilizer comprises a second low polarity polymer grafted with one or more functional groups. The mixture is subjected to compounding conditions to form a polymer product having a dispersed phase of domains of the high polarity polymer in a matrix phase of the first low polarity polymer. Methods for producing such compositions by recycling barrier films are also provided, wherein the barrier film comprises at least one layer of the first low polarity polymer and at least one layer comprising the high polarity polymer, as described above.
    Type: Application
    Filed: April 8, 2024
    Publication date: October 10, 2024
    Applicant: Equistar Chemicals, LP
    Inventors: Gang Zhang, Hrishikesh R. Munj, Mick C. Hundley
  • Patent number: 12114560
    Abstract: A carbon nanotube composite structure includes a carbon nanotube and a film-like structure. The carbon nanotube includes a p-type portion and an n-type portion. The film-like structure is a molybdenum disulfide film or a tungsten disulfide film, and the film-like structure covers the n-type portion.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: October 8, 2024
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Gao-Tian Lu, Yang Wei, Shou-Shan Fan, Yue-Gang Zhang
  • Patent number: 12107046
    Abstract: Provided is an L-shaped stepped word line structure including: L-shaped word line units, each including a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction. A word line terminal included in the short side is formed in a stepped stacked layer structure including stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region including a short side region surface/internal metal layer respectively located on a surface/in an interior. In a first direction, a length of the short side region surface metal layer is greater than that of the short side region internal metal layer, and the word line terminal corresponds to the short side region surface metal layer.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 1, 2024
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Gang Zhang, Zongliang Huo
  • Publication number: 20240303962
    Abstract: A method of determining an image feature, an electronic device, and a storage medium are provided, which relate to the field of artificial intelligence technology, in particular to fields of computer vision and depth learning technology, and may be applied to scenarios such as image processing and image recognition. The method includes: dividing an original image into a plurality of local images as an image to be processed, and each local image includes a plurality of image blocks; determining a local feature of the image to be processed according to a relationship between each image block in each local image; and determining a global feature of the image to be processed according to a relationship between a first image block at a preset position in a local image and one or more second image blocks at the preset position in other local images of the plurality of local images.
    Type: Application
    Filed: April 22, 2022
    Publication date: September 12, 2024
    Applicant: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventors: Bi LI, Nan PENG, Teng XI, Gang ZHANG
  • Publication number: 20240265687
    Abstract: A method of fusing an image feature, an electronic device, and a storage medium are provided, which relate to the field of artificial intelligence, in particular to fields of computer vision and depth learning, and may be applied to scenarios such as image processing and image recognition. The method includes: inputting an image into a first image processing model among N serially connected image processing models, to obtain an output feature of the first image processing model, an i-th image processing model includes a first shared layer to an i-th shared layer, i=1, . . . , N, and N is a natural number greater than or equal to 2; inputting an output feature of a j-th image processing model into a (j+1)-th image processing model, to obtain an output feature of the (j+1)-th image processing model, j=1, . . . , N?1; and fusing the output features of the N image processing models.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 8, 2024
    Applicant: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventors: Bi LI, Nan PENG, Teng XI, Gang ZHANG
  • Patent number: D1032701
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: June 25, 2024
    Inventors: Seyou Lei, Yubin Ou, Jianhua Lei, Gang Zhang