Patents by Inventor Gangaikondan Subramani Visweswaran
Gangaikondan Subramani Visweswaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9524242Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.Type: GrantFiled: January 28, 2014Date of Patent: December 20, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Piyush Jain, Harsh Rawat, Gangaikondan Subramani Visweswaran
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Patent number: 9305633Abstract: Embodiments include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts.Type: GrantFiled: May 20, 2014Date of Patent: April 5, 2016Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Patent number: 9177637Abstract: A dual rail SRAM array includes a plurality of columns of memory cells each coupled between two bit lines. A sense amplifier is coupled between each pair of bit lines. Capacitors are positioned between the sense amplifier outputs and the bit lines, thereby separating the sense amplifier from the bit lines. The memory cells are powered with an array supply voltage. The sense amplifier is powered with a peripheral supply voltage. During a read operation of the memory array, the bit lines are precharged to the array supply voltage. The sense amplifier is precharged to the peripheral supply voltage or to an intermediate voltage.Type: GrantFiled: August 28, 2014Date of Patent: November 3, 2015Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Publication number: 20150302917Abstract: Embodiments of the present disclosure include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts.Type: ApplicationFiled: May 20, 2014Publication date: October 22, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Publication number: 20150212945Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.Type: ApplicationFiled: January 28, 2014Publication date: July 30, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Piyush Jain, Harsh Rawat, Gangaikondan Subramani Visweswaran
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Patent number: 8982651Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.Type: GrantFiled: March 28, 2013Date of Patent: March 17, 2015Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Patent number: 8724374Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.Type: GrantFiled: October 18, 2012Date of Patent: May 13, 2014Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Publication number: 20140112081Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.Type: ApplicationFiled: October 18, 2012Publication date: April 24, 2014Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Patent number: 8654570Abstract: A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode.Type: GrantFiled: December 29, 2011Date of Patent: February 18, 2014Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Publication number: 20130170289Abstract: A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
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Patent number: 7893671Abstract: A regulator to provide an output voltage of a constant level at an output node. In an embodiment, the regulator contains a pass transistor to provide a conductive path between a pair of terminals, with the resistance offered by the path being determined by a control voltage on a third terminal of the pass transistor and the conductive path coupling a first reference potential (e.g., power supply) to the output node. An amplifier generates the control voltage based on a difference of a reference voltage and a voltage proportionate to the output voltage. A control unit turns on a current source when the voltage at the output node is below the desired constant level and turns on a current sink when voltage at said output node is above the constant level, to quickly correct for any variations in the output voltage due to load changes.Type: GrantFiled: March 5, 2008Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventors: Paramjeet Singh Sahni, Gangaikondan Subramani Visweswaran
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Patent number: 7714651Abstract: A rail-to-rail amplifier is provided. The rail-to-rail amplifier includes a p-type differential pair, an n-type differential pair, switches, and an output stage. The switches are arranged to selectively couple either the p-type differential pair or the n-type differential pair to the output stage so that only one of the differential pairs is coupled to the output stage at a time.Type: GrantFiled: February 1, 2008Date of Patent: May 11, 2010Assignee: National Semiconductor CorporationInventors: Sumant Bapat, Ansuya P. Bhatt, Surya Sharma, Gangaikondan Subramani Visweswaran
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Publication number: 20090115517Abstract: A rail-to-rail amplifier is provided. The rail-to-rail amplifier includes a p-type differential pair, an n-type differential pair, switches, and an output stage. The switches are arranged to selectively couple either the p-type differential pair or the n-type differential pair to the output stage so that only one of the differential pairs is coupled to the output stage at a time.Type: ApplicationFiled: February 1, 2008Publication date: May 7, 2009Applicant: National Semiconductor CorporationInventors: Sumant Bapat, Ansuya P. Bhatt, Surya Sharma, Gangaikondan Subramani Visweswaran
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Publication number: 20080224679Abstract: A regulator to provide an output voltage of a constant level at an output node. In an embodiment, the regulator contains a pass transistor to provide a conductive path between a pair of terminals, with the resistance offered by the path being determined by a control voltage on a third terminal of the pass transistor and the conductive path coupling a first reference potential (e.g., power supply) to the output node. An amplifier generates the control voltage based on a difference of a reference voltage and a voltage proportionate to the output voltage. A control unit turns on a current source when the voltage at the output node is below the desired constant level and turns on a current sink when voltage at said output node is above the constant level, to quickly correct for any variations in the output voltage due to load changes.Type: ApplicationFiled: March 5, 2008Publication date: September 18, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Paramjeet Singh Sahni, Gangaikondan Subramani Visweswaran