Patents by Inventor Gangfeng Ye
Gangfeng Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11239321Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has an improved barrier layer for p-GaN block layer and enhanced Ohmic contact with source. In one embodiment, regrowth of lateral channel is provided so that counter doping surface Mg will be buried. In another embodiment, a dielectric layer is provided to protect p-type block layer during the processing, and later make Ohmic source and p-type block layer. Method of a barrier regrown layer for enhanced lateral channel performance is provided where a regrown barrier layer is deposited over the drift layer. The barrier regrown layer is an anti-p-doping layer. Method of a patterned regrowth for enhanced Ohmic contact is provided where a patterned masked is used for the regrowth.Type: GrantFiled: December 6, 2019Date of Patent: February 1, 2022Inventor: Gangfeng Ye
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Patent number: 10971587Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.Type: GrantFiled: December 6, 2019Date of Patent: April 6, 2021Inventor: Gangfeng Ye
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Patent number: 10854727Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.Type: GrantFiled: February 13, 2020Date of Patent: December 1, 2020Assignee: NEXGEN POWER SYSTEMS, INC.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
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Publication number: 20200273965Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65° . The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.Type: ApplicationFiled: February 13, 2020Publication date: August 27, 2020Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
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Publication number: 20200119148Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has an improved barrier layer for p-GaN block layer and enhanced Ohmic contact with source. In one embodiment, regrowth of lateral channel is provided so that counter doping surface Mg will be buried. In another embodiment, a dielectric layer is provided to protect p-type block layer during the processing, and later make Ohmic source and p-type block layer. Method of a barrier regrown layer for enhanced lateral channel performance is provided where a regrown barrier layer is deposited over the drift layer. The barrier regrown layer is an anti-p-doping layer. Method of a patterned regrowth for enhanced Ohmic contact is provided where a patterned masked is used for the regrowth.Type: ApplicationFiled: December 6, 2019Publication date: April 16, 2020Inventor: Gangfeng Ye
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Publication number: 20200111878Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventor: Gangfeng Ye
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Patent number: 10566439Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.Type: GrantFiled: May 28, 2019Date of Patent: February 18, 2020Assignee: NEXGEN POWER SYSTEMS, INC.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
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Patent number: 10535741Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.Type: GrantFiled: January 29, 2018Date of Patent: January 14, 2020Inventor: Gangfeng Ye
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Patent number: 10535740Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has an improved barrier layer for p-GaN block layer and enhanced Ohmic contact with source. In one embodiment, regrowth of lateral channel is provided so that counter doping surface Mg will be buried. In another embodiment, a dielectric layer is provided to protect p-type block layer during the processing, and later make Ohmic source and p-type block layer. Method of a barrier regrown layer for enhanced lateral channel performance is provided where a regrown barrier layer is deposited over the drift layer. The barrier regrown layer is an anti-p-doping layer. Method of a patterned regrowth for enhanced Ohmic contact is provided where a patterned masked is used for the regrowth.Type: GrantFiled: January 29, 2018Date of Patent: January 14, 2020Inventor: Gangfeng Ye
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Publication number: 20190348522Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.Type: ApplicationFiled: May 28, 2019Publication date: November 14, 2019Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
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Patent number: 10347736Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.Type: GrantFiled: September 6, 2017Date of Patent: July 9, 2019Assignee: Nexgen Power Systems, Inc.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
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Publication number: 20180219071Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has an improved barrier layer for p-GaN block layer and enhanced Ohmic contact with source. In one embodiment, regrowth of lateral channel is provided so that counter doping surface Mg will be buried. In another embodiment, a dielectric layer is provided to protect p-type block layer during the processing, and later make Ohmic source and p-type block layer. Method of a barrier regrown layer for enhanced lateral channel performance is provided where a regrown barrier layer is deposited over the drift layer. The barrier regrown layer is an anti-p-doping layer. Method of a patterned regrowth for enhanced Ohmic contact is provided where a patterned masked is used for the regrowth.Type: ApplicationFiled: January 29, 2018Publication date: August 2, 2018Inventor: Gangfeng Ye
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Publication number: 20180219072Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.Type: ApplicationFiled: January 29, 2018Publication date: August 2, 2018Inventor: Gangfeng Ye
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Publication number: 20180166556Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.Type: ApplicationFiled: September 6, 2017Publication date: June 14, 2018Applicant: Nexgen Power Systems, Inc.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
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Publication number: 20170133481Abstract: A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.Type: ApplicationFiled: May 17, 2016Publication date: May 11, 2017Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Gangfeng Ye
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Patent number: 9368582Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.Type: GrantFiled: November 4, 2013Date of Patent: June 14, 2016Assignee: Avogy, Inc.Inventors: Isik C. Kizilyalli, David P. Bour, Thomas R. Prunty, Gangfeng Ye
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Publication number: 20150123138Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.Type: ApplicationFiled: November 4, 2013Publication date: May 7, 2015Applicant: AVOGY, INC.Inventors: Isik C. Kizilyalli, David P. Bour, Thomas R. Prunty, Gangfeng Ye