Patents by Inventor Gangning Wang
Gangning Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10615259Abstract: A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.Type: GrantFiled: November 20, 2017Date of Patent: April 7, 2020Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Li Liu, Xianyong Pu, Guangli Yang, Gangning Wang, ChiChung Tai, Hong Sun
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Publication number: 20180076284Abstract: A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Inventors: Li LIU, Xianyong PU, Guangli YANG, Gangning WANG, ChiChung TAI, Hong SUN
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Patent number: 9859372Abstract: A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.Type: GrantFiled: January 5, 2016Date of Patent: January 2, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Li Liu, Xianyong Pu, Guangli Yang, Gangning Wang, ChiChung Tai, Hong Sun
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Patent number: 9837323Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active region, a second active region, a third active region, and a fourth active region in the semiconductor substrate; and forming a middle-voltage P well region (MVPW) in each of the first active region and the second region simultaneously and forming a middle-voltage N well (MVNW) region in each of the third active region and the fourth active region simultaneously.Type: GrantFiled: June 29, 2016Date of Patent: December 5, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Chih Chun Tai, Lei Fang, Dae Sub Jung, Gangning Wang, Guangli Yang, Jiao Wang, Hong Sun, Yunpeng Peng
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Patent number: 9824914Abstract: A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, and each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers.Type: GrantFiled: February 21, 2017Date of Patent: November 21, 2017Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Guangli Yang, Xianyong Pu, Li Liu, Chihchung Tai, Gangning Wang, Hong Sun
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Publication number: 20170162433Abstract: A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, and each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Inventors: Guangli Yang, Xianyong Pu, Li Liu, Chihchung Tai, Gangning Wang, Hong Sun
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Patent number: 9653600Abstract: A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.Type: GrantFiled: February 2, 2016Date of Patent: May 16, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: GuoHao Cao, Guangli Yang, Yang Zhou, GangNing Wang
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Patent number: 9653344Abstract: A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers.Type: GrantFiled: October 13, 2015Date of Patent: May 16, 2017Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Guangli Yang, Xianyong Pu, Li Liu, Chihchung Tai, Gangning Wang, Hong Sun
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Publication number: 20170005094Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active region, a second active region, a third active region, and a fourth active region in the semiconductor substrate; and forming a middle-voltage P well region (MVPW) in each of the first active region and the second region simultaneously and forming a middle-voltage N well (MVNW) region in each of the third active region and the fourth active region simultaneously.Type: ApplicationFiled: June 29, 2016Publication date: January 5, 2017Inventors: CHIH CHUN TAI, LEI FANG, DAE SUB JUNG, GANGNING WANG, GUANGLI YANG, JIAO WANG, HONG SUN, YUNPENG PENG
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Publication number: 20160211320Abstract: A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.Type: ApplicationFiled: January 5, 2016Publication date: July 21, 2016Inventors: Li LIU, Xianyong PU, Guangli YANG, Gangning WANG, ChiChung TAI, Hong SUN
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Publication number: 20160149035Abstract: A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.Type: ApplicationFiled: February 2, 2016Publication date: May 26, 2016Inventors: GuoHao CAO, Guangli YANG, Yang ZHOU, GangNing WANG
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Publication number: 20160111321Abstract: A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers.Type: ApplicationFiled: October 13, 2015Publication date: April 21, 2016Inventors: GUANGLI YANG, XIANYONG PU, LI LIU, CHIHCHUNG TAI, GANGNING WANG, SUN HONG
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Patent number: 9287397Abstract: A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.Type: GrantFiled: July 22, 2013Date of Patent: March 15, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: GuoHao Cao, Guangli Yang, Yang Zhou, GangNing Wang
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Patent number: 9159785Abstract: Semiconductor devices having a buried layer and methods for forming the same are disclosed. In an exemplary method, a hard mask layer can be provided on a semiconductor substrate. The hard mask layer can have a plurality of through-openings. A plurality of deep trenches can be formed in the semiconductor substrate using the hard mask layer as a mask. A bottom of each of the plurality of deep trenches in the semiconductor substrate can be doped to form a plurality of heavily-doped regions. One or more of the plurality of heavily-doped regions can be connected to form the buried layer in the semiconductor substrate. There is thus no need to use an epitaxial process to form active regions. In addition, lateral isolation structures can be simultaneously formed in the semiconductor substrate.Type: GrantFiled: September 7, 2013Date of Patent: October 13, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Jiwei He, Gangning Wang, Shannon Pu, Mike Tang, Amy Feng
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Patent number: 9112025Abstract: Various embodiments provide LDMOS devices and fabrication methods. An N-type buried isolation region is provided in a P-type substrate. A P-type epitaxial layer including a first region and a second region is formed over the P-type substrate. The first region is positioned above the N-type buried isolation region, and the second region surrounds the first region. An annular groove is formed in the second region to surround the first region and to expose a surface of the N-type buried isolation region. Isolation layers are formed on both sidewalls of the annular groove. An annular conductive plug is formed in the annular groove between the isolation layers. The annular conductive plug is in contact with the N-type buried isolation region at the bottom of the annular conductive plug. A gate structure of an LDMOS transistor is formed over the first region of the P-type epitaxial layer.Type: GrantFiled: April 8, 2014Date of Patent: August 18, 2015Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Gangning Wang, Chih-Chung Tai, Guangli Yang, Jiwei He, Xianyong Pu
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Publication number: 20150179571Abstract: A method is provided for fabricating a metal interconnection structure. The method includes providing a semiconductor substrate having an active region and an isolation structure surrounding the active region; and forming a metal layer on a surface of the semiconductor substrate. The method also includes forming a metal silicide layer on the active region by a reaction of the metal layer and material of the active regions; and forming an inter metal connection layer electrically connecting with the active regions on the isolation structure. Further, the method includes forming a dielectric layer covering the metal silicide layer, the isolation structure and the inter metal connection layer on the semiconductor substrate; and forming a metal contact via electrically connecting with the active region through the inter metal connection layer in the dielectric layer.Type: ApplicationFiled: August 14, 2014Publication date: June 25, 2015Inventors: XIANYONG PU, ZONGGAO CHEN, GANGNING WANG, YIQUN CHEN
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Publication number: 20150041893Abstract: Various embodiments provide LDMOS devices and fabrication methods. An N-type buried isolation region is provided in a P-type substrate. A P-type epitaxial layer including a first region and a second region is formed over the P-type substrate. The first region is positioned above the N-type buried isolation region, and the second region surrounds the first region. An annular groove is formed in the second region to surround the first region and to expose a surface of the N-type buried isolation region. Isolation layers are formed on both sidewalls of the annular groove. An annular conductive plug is formed in the annular groove between the isolation layers. The annular conductive plug is in contact with the N-type buried isolation region at the bottom of the annular conductive plug. A gate structure of an LDMOS transistor is formed over the first region of the P-type epitaxial layer.Type: ApplicationFiled: April 8, 2014Publication date: February 12, 2015Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: GANGNING WANG, CHIH-CHUNG TAI, GUANGLI YANG, JIWEI HE, XIANYONG PU
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Publication number: 20140145267Abstract: A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.Type: ApplicationFiled: July 22, 2013Publication date: May 29, 2014Inventors: GuoHao CAO, Guangli YANG, Yang ZHOU, GangNing WANG
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Publication number: 20140077342Abstract: Semiconductor devices having a buried layer and methods for forming the same are disclosed. In an exemplary method, a hard mask layer can be provided on a semiconductor substrate. The hard mask layer can have a plurality of through-openings. A plurality of deep trenches can be formed in the semiconductor substrate using the hard mask layer as a mask. A bottom of each of the plurality of deep trenches in the semiconductor substrate can be doped to form a plurality of heavily-doped regions. One or more of the plurality of heavily-doped regions can be connected to form the buried layer in the semiconductor substrate. There is thus no need to use an epitaxial process to form active regions. In addition, lateral isolation structures can be simultaneously formed in the semiconductor substrate.Type: ApplicationFiled: September 7, 2013Publication date: March 20, 2014Applicant: Semiconductor Manufacturing International Corp.Inventors: JIWEI HE, GANGNING WANG, SHANNON PU, MIKE TANG, AMY FENG
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Patent number: 7977734Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easy to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching. Thus, no polysilicon residue will be formed on the sidewall of the dielectric layer.Type: GrantFiled: July 14, 2009Date of Patent: July 12, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Haitao Jiang, Xinsheng Zhong, Jiangpeng Xue, Gangning Wang