Abstract: A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.

Abstract: A data processing method includes the following steps: a processor receives a symmetric wrapping key, and when an application needs to use a user private key, the processor executes an encryption and decryption instruction in a hardware-acceleration instruction-set. The encryption and decryption instruction is configured to apply the symmetric wrapping key to decrypt a wrapped private key that corresponds to the application to obtain the user private key. In addition, the symmetric wrapping key is stored in a model specific register of the processor.

Abstract: A data processing method includes the following steps: a processor receives a symmetric wrapping key, and when an application needs to use a user private key, the processor executes an encryption and decryption instruction in a hardware-acceleration instruction-set. The encryption and decryption instruction is configured to apply the symmetric wrapping key to decrypt a wrapped private key that corresponds to the application to obtain the user private key. In addition, the symmetric wrapping key is stored in a model specific register of the processor.

Abstract: A chipset and a host controller, including a storage host controller for a storage device and an encryption and decryption engine that is implemented by hardware. The storage host controller analyzes a write command to obtain write command information, and provides the write command information and write data to the encryption and decryption engine. The encryption and decryption engine combines a data drive key with the write command information to encrypt the write data and provides the encrypted write data to the storage host controller to be written into a storage device via a communication port.

Abstract: A chipset and a host controller, including a storage host controller for a storage device and an encryption and decryption engine that is implemented by hardware. The storage host controller analyzes a write command to obtain write command information, and provides the write command information and write data to the encryption and decryption engine. The encryption and decryption engine combines a data drive key with the write command information to encrypt the write data and provides the encrypted write data to the storage host controller to be written into a storage device via a communication port.