Patents by Inventor GANGYAO WANG

GANGYAO WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11368150
    Abstract: A device includes an output circuit configured to drive a gate of a field effect transistor (FET) in response to a drive signal. The FET includes a body diode. Control logic is configured to generate the drive signal to control the output circuit to drive the FET. A measurement circuit is configured to sample a first voltage across the FET in response to a first state of the drive signal and configured to sample a second voltage across the FET in response to a second state of the drive signal. The second state of the drive signal is different from the first state. The control logic is configured to determine a difference between the first voltage and a reference voltage. The control logic is configured to compare the difference to a degradation threshold to determine a level of degradation of the FET. The reference voltage is determined based on the second voltage.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gangyao Wang, Xiong Li, Suxuan Guo
  • Patent number: 11070197
    Abstract: Methods, apparatus, systems and articles of manufacture are described for transistor health monitoring. An example gate driver includes a request receiver pin, a measurement transmitter pin, and a driver control logic pin, the request receiver pin, the measurement transmitter pin, and the driver control logic pin configured to be coupled to a controller, a sensing pin, the sensing pin to be coupled to a sensing circuit, a control logic circuit having an input coupled to the request receiver pin, a transistor coupled to the control logic circuit and the sensing pin, a multiplexer coupled to the control logic circuit and the sensing pin, an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin, and a driver control logic circuit coupled to the driver control logic pin.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gangyao Wang, Rajarshi Mukhopadhyay, Miguel Aguirre
  • Publication number: 20210203309
    Abstract: Methods, apparatus, systems and articles of manufacture are described for transistor health monitoring. An example gate driver includes a request receiver pin, a measurement transmitter pin, and a driver control logic pin, the request receiver pin, the measurement transmitter pin, and the driver control logic pin configured to be coupled to a controller, a sensing pin, the sensing pin to be coupled to a sensing circuit, a control logic circuit having an input coupled to the request receiver pin, a transistor coupled to the control logic circuit and the sensing pin, a multiplexer coupled to the control logic circuit and the sensing pin, an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin, and a driver control logic circuit coupled to the driver control logic pin.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: Gangyao Wang, Rajarshi Mukhopadhyay, Miguel Aguirre
  • Publication number: 20200235731
    Abstract: A device includes an output circuit configured to drive a gate of a field effect transistor (FET) in response to a drive signal. The FET includes a body diode. Control logic is configured to generate the drive signal to control the output circuit to drive the FET. A measurement circuit is configured to sample a first voltage across the FET in response to a first state of the drive signal and configured to sample a second voltage across the FET in response to a second state of the drive signal. The second state of the drive signal is different from the first state. The control logic is configured to determine a difference between the first voltage and a reference voltage. The control logic is configured to compare the difference to a degradation threshold to determine a level of degradation of the FET. The reference voltage is determined based on the second voltage.
    Type: Application
    Filed: August 29, 2019
    Publication date: July 23, 2020
    Inventors: GANGYAO WANG, XIONG LI, SUXUAN GUO