Abstract: A display system includes a light modulator divided into an array of individually controllable pixels and an input-driven illumination device. The illumination device is adapted to receive a variable input and is configured to direct light of variable intensity onto the modulator, depending on the input. The display system further includes a calibrating arrangement for establishing the input to the illumination device to produce a desired intensity level of light. The calibrating arrangement includes a light sensing mechanism, which senses the light from the illumination device while the illumination device is driven by an initial input. The calibration arrangement is configured to determine a comparison between the sensed light and a value representative of the desired-intensity level. The calibration arrangement further includes a control arrangement responsive to the comparison for varying the input so as to provide light of the desired intensity level.

Abstract: A miniature display system has polarized beam reflector film and display panel pivotally attached to the polarized beam reflector film. Because these components are pivotally attached, the components can be folded, thereby reducing the bulk of the display system. The display system may include other components such as light source, curved reflector, quarter wave film, or conic mirror. These components may also be pivotally attached to each other or to the polarized beam reflector film or the display panel.

Abstract: A display system has light source, display panel, conic mirror, and polarized reflector. The light from the light source is filtered by a diffuse reflective polarizer to contain light in a first linear polarization (for example, s-polarized light). That light is directed by the conic mirror toward the polarized reflector, and is reflected toward the display panel displaying images. The conic mirror and the polarized reflector is shaped such that the light telecentrically and uniformly illuminates the display panel. The light is reflected from the display panel being patterned by the image and rotated into a second linear polarization (for example, p-polarized light). The rotated light passes through the polarized reflector for viewing.

Abstract: A light emitting diode (LED) driver pad comprising a multiplying digital to analog converter (MDAC), which allows for differing LED characteristics to be matched digitally. Either a plurality of MDACs are integrated onto a single integrated circuit, one MDAC per color of LED, or a single MDAC may be multiplexed to drive a plurality of different color LEDs. The MDAC allows for LED operating current to be set digitally, while allowing an overall brightness or intensity control, thus achieving uniform color balance over a range of operating characteristics.

Abstract: A miniature display system has light source, display panel, polarized beam reflector film, curved reflector, and quarter wave film. The light source supplies light polarized in a first direction. The light from the light source reflects off the polarized beam reflector film and impinges the display panel. The polarized beam reflector film is configured to reflect light polarized in the first direction but pass the light polarized in a second direction orthogonal to the first direction. The display panel produces images on its surface (“display surface”). The light hitting the display panel is reflected orthogonally (polarized in a second direction) and bearing the image, thus bearing a pattern. The modulated light passes through the polarized beam reflector film and is reflected on a curved reflector. The quarter wave film is disposed between the polarized beam reflector film and the curved reflector.

Abstract: Precompensated NRZ-encoded data for writing to magnetic storage medium operates with multiple NRZI-to-NRZ decoders that are each supplied with a selectably-variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements operating with D-flip flops and charge pumps in a delay-locked feedback loop. The direction of current supplied to or from a capacitor by the charge-pump during a cycle of delayed clock signal is controlled by the delayed clock signal for shaping the feedback signal to trigger appropriately the next cycle of the delayed clock signal. The duration of the selectable delay is adjusted by setting the amplitudes of the charge and discharge currents supplied by the charge-pump. Stable delayed versions of the master clock promote reliable conversions of NRZI data to write precompensated NRZ recordable data.

Abstract: Low-noise magneto-resistive (MR) pre-amplifier circuit amplifies signal from MR head. MR head is biased at optimal point by current source to generate signal. Current source is powered by regulator to reduce noise contribution from Vcc due to finite output impedance of current source. Self-biased CMOS low-noise amplifier (LNA) minimizes input-referred noised without using negative power supply. Small MOS transistor with feedback tracking loop replaces self-bias resistor which determines lower corner cutoff frequency. This facilitates use of large-value resistor, thereby enabling on-chip integration of DC blocking input capacitor. Gm—Gm amplifier configuration increases gain bandwidth product and minimizes parasitic effects of MOS transistors.

Abstract: Precompensated NRZ-encoded data for writing to magnetic storage medium operates with multiple NRZI-to-NRZ decoders that are each supplied with a selectably-variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements operating with D-flip flops and charge pumps in a delay-locked feedback loop. The direction of current supplied to or from a capacitor by the charge-pump during a cycle of delayed clock signal is controlled by the delayed clock signal for shaping the feedback signal to trigger appropriately the next cycle of the delayed clock signal. The duration of the selectable delay is adjusted by setting the amplitudes of the charge and discharge currents supplied by the charge-pump. Stable delayed versions of the master clock promote reliable conversions of NRZI data to write precompensated NRZ recordable data.

Abstract: A variable gain amplifier includes a differentially-connected pair of NFETs for receiving differential input voltage signals. The source-drain channel of each NFET is coupled to a respective PFET operating in linear mode as a variable load resistance in a g.sub.m .times.R gain stage, the gain of which is determined by a gain-controlling signal applied to the gates of the PFETs. For broad dynamic range of voltage amplification, the drain of each NFET is coupled to a respective current source that is referenced to a supply voltage having a higher voltage level than the supply voltage for biasing the PFETs. Multiple stages of such variable gain stages are cascaded and independently gain controlled in successive stages to yield substantially exponential variation in overall gain as individual gain stages are adjusted. A control circuit controls the gains of each stage for obtaining a desired total overall gain for the multi-stage amplifier.

Abstract: A write driver for an inductive head of a magnetic storage medium that induces a faster write current switch across an inductive head element of a magnetic storage medium comprising having a pair of switches, S.sub.1 and S.sub.2, coupled to a pair of current sources, I.sub.1 and I.sub.2, wherein first switch S.sub.1 is coupled to first current source I.sub.1 and controlled by a first current switch control signal CLK. Second switch S.sub.2 is coupled to second current source I.sub.2 and controlled by second current switch control signal /CLK. First switch S.sub.1 is also controlled by first current control signal CLK to maximize rail to rail voltage swing. Similarly, second switch S.sub.2 is also controlled by second current control signal /CLK. In an alternative embodiment, a current booster is coupled to each current source to boost the write current to offset the otherwise decrease to write current due to damping resistor R.sub.